公开(公告)号：US5061649A

公开(公告)日：1991-10-29

申请号：US29954

申请日：1987-03-25

申请人： Naoko Takenouchi ,  Katsuhiko Hieda

发明人： Naoko Takenouchi ,  Katsuhiko Hieda

IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L29/78

摘要： A semiconductor integrated circuit device is disclosed which has an MOSFET with a lightly doped drain or LLD structure. A gate electrode layer is insulatively provided above a semiconductor substrate of p conductivity type. Source and drain layers of n conductivity type are formed in the substrate in such a manner as to be substantially self-aligned with the gate electrode. Each of these source and drain layers is comprised of a heavily doped diffusion layer and a lightly doped diffusion layer. The n- diffusion layer is deep enough to fully surround the heavily doped layer in the substrate. The n- diffusion layer has a step-like cross-section, whereby the effective channel length of MOSFET is increased inside the substrate to increase the punch-through voltage level.

摘要翻译： 公开了一种具有轻掺杂漏极或LLD结构的MOSFET的半导体集成电路器件。 在p型导电型的半导体衬底之上绝缘地设置栅电极层。 n导电型的源极和漏极层以与栅电极基本上自对准的方式形成在衬底中。 这些源极和漏极层中的每一个由重掺杂扩散层和轻掺杂扩散层组成。 n-扩散层足够深以完全围绕衬底中的重掺杂层。 n-扩散层具有阶梯状横截面，由此在衬底内增加MOSFET的有效沟道长度以增加穿通电压电平。

公开(公告)号：US5164801A

公开(公告)日：1992-11-17

申请号：US790066

申请日：1991-11-12

申请人： Katsuhiko Hieda ,  Kazumasa Sunouchi ,  Akihiro Nitayama ,  Kazushi Tsuda ,  Hiroshi Takato ,  Naoko Takenouchi

发明人： Katsuhiko Hieda ,  Kazumasa Sunouchi ,  Akihiro Nitayama ,  Kazushi Tsuda ,  Hiroshi Takato ,  Naoko Takenouchi

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/823864 ,  H01L27/0623 ,  H01L27/092 ,  H01L29/78 ,  Y10S257/90

摘要： A P channel MIS type semiconductor device have P type source and drain regions formed in a N type semiconductor substrate. Each source and drain regions are constructed the low and high impurity concentration layers. Channel side edges of the low concentration impurity layers arranged inside of the high concentration impurity layers. These double layer source and drain structure prevent the off set gate construction and the parasitic resistance.

摘要翻译： P沟道MIS型半导体器件具有形成在N型半导体衬底中的P型源区和漏区。 每个源极和漏极区域被构造为低和高杂质浓度层。 低浓度杂质层的通道侧边缘布置在高浓度杂质层的内部。 这些双层源极和漏极结构防止了闭合栅极结构和寄生电阻。

公开(公告)号：US07759174B2

公开(公告)日：2010-07-20

申请号：US11657088

申请日：2007-01-24

申请人： Katsuhiko Hieda

发明人： Katsuhiko Hieda

IPC分类号： H01L21/8232 ,  H01L21/335

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L29/66825 ,  Y10S257/905

摘要： A semiconductor device includes a substrate including a semiconductor and a trench, and an electrically rewritable semiconductor memory cell on the substrate, the semiconductor memory cell comprising a charge storage layer including an upper surface and a lower surface, an area of the lower surface being smaller than an area of the upper surface, and at least a part of the charge storage layer being provided in the trench, first insulating layer between the lower surface of the charge storage layer and a bottom surface of the trench, second insulating layer between a side surface of the trench and a side surface of the charge storage layer and between the side surface of the trench and a side surface of the first insulating layer, third insulating layer on the charge storage layer, and a control gate electrode on the third insulating layer.

摘要翻译： 半导体器件包括：衬底，其包括半导体和沟槽;以及在该衬底上的电可重写半导体存储单元，所述半导体存储单元包括电荷存储层，所述电荷存储层包括上表面和下表面，所述下表面的面积较小 比电荷存储层的下表面和沟槽的底面之间的第一绝缘层设置在沟槽中的电荷存储层的至少一部分，第二绝缘层在侧面 沟槽的表面和电荷存储层的侧表面和沟槽的侧表面与第一绝缘层的侧表面之间，电荷存储层上的第三绝缘层和第三绝缘层上的控制栅极电极 。

公开(公告)号：US07071107B2

公开(公告)日：2006-07-04

申请号：US10674382

申请日：2003-10-01

申请人： Katsuhiko Hieda ,  Atsuko Kawasaki ,  Masahiro Kiyotoshi ,  Katsuhiko Tachibana ,  Soichi Yamazaki

发明人： Katsuhiko Hieda ,  Atsuko Kawasaki ,  Masahiro Kiyotoshi ,  Katsuhiko Tachibana ,  Soichi Yamazaki

IPC分类号： H01L21/302

CPC分类号： H01L21/02222 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02318 ,  H01L21/02337 ,  H01L21/31111 ,  H01L21/3125 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/31683 ,  H01L21/76224 ,  H01L21/76229

摘要： There is disclosed a method of manufacturing a semiconductor device, wherein an Si3N4 film is formed as a mask member on the surface of a silicon substrate, then etched to form an STI trench. A solution of perhydrogenated silazane polymer is coated on the surface of the silicon substrate having an STI trench formed thereon to deposit a coated film (PSZ film) thereon. The PSZ film deposited on the mask member is removed, leaving part of the PSZ film inside the trench, wherein the thickness of the PSZ film is controlled to make the height thereof from the bottom of the STI trench become 600 nm or less. Thereafter, the PSZ film is heat-treated in a water vapor-containing atmosphere to convert the PSZ film into a silicon oxide film through a chemical reaction of the PSZ film. Subsequently, the silicon oxide film is heat-treated to densify the silicon oxide film.

摘要翻译： 公开了一种制造半导体器件的方法，其中在硅衬底的表面上形成Si 3 N 4 N 4膜作为掩模构件，然后蚀刻形成 一个STI沟槽。 将过氢化硅氮烷聚合物的溶液涂布在其上形成有STI沟槽的硅衬底的表面上，以在其上沉积涂膜（PSZ膜）。 去除沉积在掩模构件上的PSZ膜，使PSZ膜的一部分留在沟槽内，其中控制PSZ膜的厚度使其从STI沟槽底部的高度变为600nm以下。 然后，在含水蒸汽的气氛中对PSZ膜进行热处理，通过PSZ膜的化学反应将PSZ膜转换为氧化硅膜。 随后，对氧化硅膜进行热处理以使氧化硅膜致密化。

公开(公告)号：US06992358B2

公开(公告)日：2006-01-31

申请号：US10874732

申请日：2004-06-24

申请人： Katsuhiko Hieda ,  Kazuya Matsuzawa ,  Daisuke Hagishima

发明人： Katsuhiko Hieda ,  Kazuya Matsuzawa ,  Daisuke Hagishima

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10829 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854 ,  H01L29/78648

摘要： Disclosed is a semiconductor device comprising an underlying insulating film having a depression, a semiconductor structure which includes a first semiconductor portion having a portion formed on the underlying insulating film and a first overlap portion which overlaps the depression, a second semiconductor portion having a portion formed on the underlying insulating film and a second overlap portion which overlaps the depression, and a third semiconductor portion disposed between the first and second semiconductor portions and having a portion disposed above the depression, wherein overlap width of the first overlap portion and overlap width of the second overlap portion are equal to each other, a gate electrode including a first electrode portion covering upper and side surfaces of the third semiconductor portion and a second electrode portion formed in the depression, and a gate insulating film interposed between the semiconductor structure and the gate electrode.

摘要翻译： 公开了一种半导体器件，包括具有凹陷的基底绝缘膜，半导体结构，其包括具有形成在下面的绝缘膜上的部分的第一半导体部分和与凹部重叠的第一重叠部分，第二半导体部分形成有部分 在第一半导体部分和第二半导体部分之间并且具有设置在该凹部之上的部分的第三半导体部分，其中第一重叠部分的重叠宽度和第二重叠部分的重叠宽度 第二重叠部分彼此相等，栅电极包括覆盖第三半导体部分的上表面和第二表面的第一电极部分和形成在凹陷部中的第二电极部分，以及插入在半导体结构和栅极之间的栅极绝缘膜 电极。

公开(公告)号：US20050224863A1

公开(公告)日：2005-10-13

申请号：US11088000

申请日：2005-03-24

申请人： Katsuhiko Hieda ,  Yoshio Ozawa

发明人： Katsuhiko Hieda ,  Yoshio Ozawa

IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/08 ,  H01L27/092 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114

摘要： A semiconductor device includes a semiconductor substrate, first isolation area on the substrate including first and second trenches, first insulating film in the trenches protruding above the surface, with respect to channel width direction, distance between first insulating film on first and second trenches at position higher than the surface being longer than the distance at a position of the surface, and a memory cell having the channel width direction and provided on the substrate including second insulating film on the surface between first and second trenches, control gate above second insulating film, floating gate between control gate and second insulating film, with respect to dimension in the direction, an upper side of floating gate facing control gate being larger than a lower side of floating gate facing second insulating film, and with respect to the direction, displacement of floating gate to first and second trenches being approximately equal.

摘要翻译： 一种半导体器件，包括半导体衬底，所述衬底上的第一隔离区域包括第一和第二沟槽，相对于沟道宽度方向在所述沟槽的上方突出的沟槽中的第一绝缘膜，位于第一和第二沟槽的位置处的第一绝缘膜之间的距离 高于所述表面的距离比所述表面的距离长;以及存储单元，具有所述沟道宽度方向并且设置在所述基板上，所述基板包括第一和第二沟槽之间的表面上的第二绝缘膜，位于第二绝缘膜上方的控制栅极， 控制栅极与第二绝缘膜之间的浮栅，相对于方向尺寸，浮置栅极面对的控制栅极的上侧大于浮置栅极面对第二绝缘膜的下侧，并且相对于方向，位移 第一和第二沟槽的浮动栅极大致相等。

公开(公告)号：US06787827B2

公开(公告)日：2004-09-07

申请号：US10132255

申请日：2002-04-26

申请人： Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

发明人： Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/42368 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在半导体衬底上的预定栅极形成区域形成虚设膜和伪栅极图案，在虚拟栅极图案的侧壁上形成第一侧壁绝缘膜，形成 在半导体衬底的围绕着具有第一侧壁绝缘膜的伪栅极图案的部分上的层间绝缘膜，通过去除伪栅极图案形成沟槽，去除通过沟槽暴露的一部分虚拟膜，同时留下一部分 第一侧壁绝缘膜以及设置在第一侧壁绝缘膜的部分下方的虚设膜的一部分，至少在槽的底面上形成栅极绝缘膜，并且在栅极绝缘上形成栅极电极 胶片形成在凹槽中。

公开(公告)号：US06750142B2

公开(公告)日：2004-06-15

申请号：US09983190

申请日：2001-10-23

申请人： Katsuhiko Hieda

发明人： Katsuhiko Hieda

IPC分类号： H01L2144

CPC分类号： H01L23/5283 ,  H01L21/76807 ,  H01L21/76816 ,  H01L23/5222 ,  H01L23/5228 ,  H01L27/10882 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate on which an element is formed, a lower wiring formed on the semiconductor substrate, and an upper wiring formed on and connected to the lower wiring. The upper wiring includes a plurality of regions having different thicknesses in a continuous wiring region excluding a connection region for connecting the upper and lower wirings.

摘要翻译： 半导体器件包括其上形成有元件的半导体衬底，形成在半导体衬底上的下布线，以及形成在下布线上并连接到下布线的上布线。 上部布线包括除了用于连接上部和下部布线的连接区域之外的连续布线区域中具有不同厚度的多个区域。

公开(公告)号：US06720606B1

公开(公告)日：2004-04-13

申请号：US09660390

申请日：2000-09-12

申请人： Akihiro Nitayama ,  Katsuhiko Hieda ,  Shigeru Ishibashi ,  Yusuke Kohyama

发明人： Akihiro Nitayama ,  Katsuhiko Hieda ,  Shigeru Ishibashi ,  Yusuke Kohyama

IPC分类号： H01L27108

CPC分类号： H01L27/10867 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/945

摘要： A semiconductor memory device has a semiconductor substrate, a first semiconductor region of a first conduction type formed on the semiconductor substrate, a second semiconductor region of a second conduction type opposite to the first conduction type, formed on the first semiconductor region. A trench capacitors having a trench extends through the first semiconductor region and the second semiconductor region, and is formed such that its top does not reach a top surface of the second semiconductor region, and the trench is formed therein with a conductive trench fill. A pair of gate electrodes is formed on the second semiconductor region, overlying the trench capacitor. A pair of insulating layers is formed to cover each of the pair of gate electrodes. A conductive layer is formed between the pair of insulating layers to self-align to each of the pair of insulating layers. The conductive layer has a leading end insulated from the second semiconductor region and reaching the interior of the second semiconductor region, and electrically connected to the conductive trench fill of the trench capacitor. A pair of third semiconductor regions of the first conduction type are formed in the second semiconductor region, and positioned opposite to each other with respect to the conductive layer. Each of the third semiconductor regions is directly in contact with the conductive layer, and constitutes either a source or a drain of transistors having one of the pair of gate electrodes, respectively. The pair of third semiconductor regions is formed substantially to a uniform depth.

摘要翻译： 半导体存储器件具有形成在第一半导体区域上的半导体衬底，形成在半导体衬底上的第一导电类型的第一半导体区域，与第一导电类型相反的第二导电类型的第二半导体区域。 具有沟槽的沟槽电容器延伸穿过第一半导体区域和第二半导体区域，并且形成为使得其顶部不到达第二半导体区域的顶表面，并且沟槽在其中形成有导电沟槽填充物。 在第二半导体区上形成一对栅电极，覆盖在沟槽电容器上。 形成一对绝缘层以覆盖该对栅电极中的每一个。 在一对绝缘层之间形成导电层，以与一对绝缘层中的每一个自对准。 导电层具有与第二半导体区域绝缘​​并到达第二半导体区域的内部的前端，并且电连接到沟槽电容器的导电沟槽填充物。 第一导电类型的一对第三半导体区域形成在第二半导体区域中，并且相对于导电层彼此相对定位。 第三半导体区域中的每一个直接与导电层接触，并且分别构成具有一对栅极电极之一的晶体管的源极或漏极。 一对第三半导体区域基本上形成为均匀的深度。

公开(公告)号：US06690054B2

公开(公告)日：2004-02-10

申请号：US10173596

申请日：2002-06-19

申请人： Jun Lin ,  Chung-Ming Chu ,  Toshiya Suzuki ,  Katsuhiko Hieda

发明人： Jun Lin ,  Chung-Ming Chu ,  Toshiya Suzuki ,  Katsuhiko Hieda

IPC分类号： H01L27108

CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/91

摘要： A method for fabricating a capacitor comprises the steps of: forming a lower electrode of a metal over a substrate; forming a capacitor dielectric film of an oxide dielectric film on the lower electrode; depositing a metal film on the capacitor dielectric film; performing a thermal processing in a hydrogen-content atmosphere after the step of depositing the metal film; and patterning the metal film to form an upper electrode of the metal film after the step of performing the thermal processing. Thus, the adhesion between the upper electrode and the capacitor dielectric film is improved, and capacitor characteristics can be improved.

摘要翻译： 制造电容器的方法包括以下步骤：在衬底上形成金属的下电极; 在下电极上形成氧化物电介质膜的电容器电介质膜; 在电容器电介质膜上沉积金属膜; 在沉积金属膜的步骤之后，在含氢气氛中进行热处理; 以及在进行热处理的步骤之后图案化金属膜以形成金属膜的上电极。 因此，改善了上电极和电容器电介质膜之间的粘附性，并且可以提高电容器特性。