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    FABRICATION METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE
    3.
    发明申请
    FABRICATION METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE 有权
    半导体封装结构的制造方法

    公开(公告)号：US20110159643A1

    公开(公告)日：2011-06-30

    申请号：US12770059

    申请日：2010-04-29

    申请人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

    发明人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

    IPC分类号： H01L21/60 ,  H01L21/56

    CPC分类号： H01L23/495 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49117 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A fabrication method of a semiconductor package structure includes: patterning a metal plate having first and second surfaces; forming a dielectric layer on the metal plate; forming a metal layer on the first surface and the dielectric layer; forming metal pads on the second surface, the metal layer having a die pad and traces each having a bond pad; mounting a semiconductor chip on the die pad, followed by connecting electrically the semiconductor chip to the bond pads through bonding wires; forming an encapsulant to cover the semiconductor chip and the metal layer; removing portions of the metal plate not covered by the metal pads so as to form metal pillars; and performing a singulation process. The fabrication method is characterized by disposing traces with bond pads close to the die pad to shorten the bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging.

    摘要翻译： 半导体封装结构的制造方法包括：图案化具有第一表面和第二表面的金属板; 在所述金属板上形成电介质层; 在所述第一表面和所述电介质层上形成金属层; 在所述第二表面上形成金属焊盘，所述金属层具有管芯焊盘并且各自具有接合焊盘; 将半导体芯片安装在芯片焊盘上，然后通过接合线将半导体芯片电连接到焊盘; 形成密封剂以覆盖半导体芯片和金属层; 去除未被金属垫覆盖的金属板的部分，以形成金属柱; 并执行单独处理。 该制造方法的特征在于，将具有接合焊盘的迹线设置在芯片焊盘附近以缩短接合线并形成从电介质层突出的金属柱，以避免焊料桥接。

    Fabrication method of semiconductor package structure
    7.
    发明授权
    Fabrication method of semiconductor package structure 有权
    半导体封装结构的制造方法

    公开(公告)号：US08304268B2

    公开(公告)日：2012-11-06

    申请号：US12770059

    申请日：2010-04-29

    申请人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

    发明人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

    IPC分类号： H01L21/44

    CPC分类号： H01L23/495 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49117 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A fabrication method of a semiconductor package structure includes: patterning a metal plate having first and second surfaces; forming a dielectric layer on the metal plate; forming a metal layer on the first surface and the dielectric layer; forming metal pads on the second surface, the metal layer having a die pad and traces each having a bond pad; mounting a semiconductor chip on the die pad, followed by connecting electrically the semiconductor chip to the bond pads through bonding wires; forming an encapsulant to cover the semiconductor chip and the metal layer; removing portions of the metal plate not covered by the metal pads so as to form metal pillars; and performing a singulation process. The fabrication method is characterized by disposing traces with bond pads close to the die pad to shorten the bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging.

    摘要翻译： 半导体封装结构的制造方法包括：图案化具有第一表面和第二表面的金属板; 在所述金属板上形成电介质层; 在所述第一表面和所述电介质层上形成金属层; 在所述第二表面上形成金属焊盘，所述金属层具有管芯焊盘并且各自具有接合焊盘; 将半导体芯片安装在芯片焊盘上，然后通过接合线将半导体芯片电连接到焊盘; 形成密封剂以覆盖半导体芯片和金属层; 去除未被金属垫覆盖的金属板的部分，以形成金属柱; 并执行单独处理。 该制造方法的特征在于，将具有接合焊盘的迹线设置在芯片焊盘附近以缩短接合线并形成从电介质层突出的金属柱，以避免焊料桥接。

    SEMICONDUCTOR PACKAGE STRUCTURE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE 有权
    半导体封装结构

    公开(公告)号：US20110156227A1

    公开(公告)日：2011-06-30

    申请号：US12770028

    申请日：2010-04-29

    申请人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

    发明人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

    IPC分类号： H01L23/495

    CPC分类号： H01L23/495 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49117 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.

    摘要翻译： 半导体封装结构包括：电介质层; 设置在电介质层上并具有芯片焊盘和迹线的金属层，每个迹线包括迹线体，延伸到管芯焊盘周边的接合焊盘和相对的迹线端; 金属柱贯穿电介质层，其一端连接到管芯焊盘并且其端部从电介质层突出; 半导体芯片，安装在芯片焊盘上，并通过接合线电连接到焊盘; 以及覆盖半导体芯片，接合线，金属层和电介质层的密封剂。 本发明的特征在于，将具有接合焊盘的迹线设置在芯片焊盘附近以缩短接合线并形成从电介质层突出的金属柱，以避免在现有技术中遇到的焊料桥接。

    Packaging substrate and fabrication method thereof
    10.
    发明授权
    Packaging substrate and fabrication method thereof 有权
    包装基板及其制造方法

    公开(公告)号：US09171741B2

    公开(公告)日：2015-10-27

    申请号：US13566265

    申请日：2012-08-03

    申请人： Wei-Ping Wang ,  Pang-Chun Lin ,  Chin-Chih Hsiao ,  Kaun-i Cheng ,  Cheng-Wen Chiu

    发明人： Wei-Ping Wang ,  Pang-Chun Lin ,  Chin-Chih Hsiao ,  Kaun-i Cheng ,  Cheng-Wen Chiu

    IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

    CPC分类号： H01L21/4857 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.

    摘要翻译： 一种用于制造封装衬底的方法，包括：提供具有形成在第一金属层上的第一金属层和第二金属层的载体; 在所述第二金属层上形成第一电路层，并在所述第二金属层的边缘上形成分离部分，使得所述分离部分与所述第一电路层隔开; 在所述第二金属层和所述第一电路层上形成介电层，使得所述第一电路层和所述分离部分嵌入在所述电介质层中，并且所述电介质层的部分形成在所述第一电路层与所述分离部之间; 在所述电介质层上形成第二电路层; 并且在分离部分上施加力以便去除第一金属层和载体，从而保持第一电路层的完整性。