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    Insulated Gate Bipolar Transistor (IGBT) Collector Formed with Ge/A1 and Production Method
    1.
    发明申请
    Insulated Gate Bipolar Transistor (IGBT) Collector Formed with Ge/A1 and Production Method 审中-公开
    绝缘栅双极晶体管（IGBT）采用Ge / A1及其制作方法

    公开(公告)号：US20100327314A1

    公开(公告)日：2010-12-30

    申请号：US12493226

    申请日：2009-06-28

    申请人： Ping Huang ,  Tao Feng ,  Ruisheng Wu ,  Yi Chen ,  Lei Duan

    发明人： Ping Huang ,  Tao Feng ,  Ruisheng Wu ,  Yi Chen ,  Lei Duan

    IPC分类号： H01L29/739 ,  H01L21/20

    CPC分类号： H01L29/7395 ,  H01L29/0834 ,  H01L29/165 ,  H01L29/66333

    摘要： This invention discloses an IGBT device with its collector formed with Ge/Al and associated method of fabrication. The collector is formed on the substrate layer, which is on the back of IGBT, and contains Ge and Al thin films. After thinning and etching the back side of IGBT substrate, Ge and Al are sequentially deposited to form Ge/Al thin films on the back surface of the substrate. An annealing process is then carried out to diffuse Al into Ge thin film layer to form a P-doped Ge layer functioning as the IGBT collector. The present invention is applicable to both non punch through IGBTs as well as punch through IGBTs.

    摘要翻译： 本发明公开了一种IGBT器件，其集电极形成Ge / Al及其制造方法。 集电体形成在IGBT背面的基板层上，并含有Ge和Al薄膜。 在对IGBT基板的背面进行变薄蚀刻之后，依次沉积Ge和Al，以在衬底的背面形成Ge / Al薄膜。 然后进行退火处理以将Al扩散到Ge薄膜层中，以形成用作IGBT集电极的P掺杂Ge层。 本发明适用于非穿通IGBT以及穿通IGBT。

    Wafer level packaging method of encapsulating the bottom and side of a semiconductor chip
    2.
    发明授权
    Wafer level packaging method of encapsulating the bottom and side of a semiconductor chip 有权
    封装半导体芯片的底部和侧面的晶片级封装方法

    公开(公告)号：US08486803B2

    公开(公告)日：2013-07-16

    申请号：US13273168

    申请日：2011-10-13

    申请人： Ping Huang ,  Ruisheng Wu ,  Lei Duan ,  Yi Chen ,  Yuping Gong

    发明人： Ping Huang ,  Ruisheng Wu ,  Lei Duan ,  Yi Chen ,  Yuping Gong

    IPC分类号： H01L21/30

    CPC分类号： H01L23/3171 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/12105 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

    摘要： A chip-scale packaging method, with bottom and side of a semiconductor chip encapsulated, includes the following steps: attaching backside of a thinned semiconductor wafer to a dicing tape; separating individual chips by cutting from front side of the wafer at scribe line but not cut through the dicing tape; flipping and attaching the wafer onto a top surface of a double-sided tape, then removing the dicing tape; attaching bottom surface of the double-sided tape on a supporting plate; filling the space between adjacent chips and covering the whole wafer backside with a molding material; flipping the whole structure and remove the supporting plate; placing solder balls at corresponding positions on electrodes of each chip and performing backflow treatment; finally separating individual chip packages by cutting through molding material at the space between adjacent chip packages with molding material encapsulating the bottom and side of each individual semiconductor chip.

    摘要翻译： 封装了半导体芯片的底部和侧面的芯片级封装方法包括以下步骤：将薄化的半导体晶片的背面安装到切割带上; 通过在切割线处切割晶片的正面而不切割切割带来分离各个芯片; 翻转并将晶片连接到双面胶带的顶表面上，然后移除切割胶带; 将双面胶带的底面附着在支撑板上; 填充相邻芯片之间的空间并用模制材料覆盖整个晶片背面; 翻转整个结构并拆下支撑板; 将焊球放置在每个芯片的电极上的相应位置，并执行回流处理; 最后通过在封装每个单独的半导体芯片的底部和侧面的成型材料之间切割相邻芯片封装之间的空间处的模制材料来分离单个芯片封装。

    WAFER LEVEL PACKAGING METHOD OF ENCAPSULATING THE BOTTOM AND SIDE OF A SEMICONDUCTOR CHIP
    3.
    发明申请
    WAFER LEVEL PACKAGING METHOD OF ENCAPSULATING THE BOTTOM AND SIDE OF A SEMICONDUCTOR CHIP 有权
    封装半导体芯片底部和底部的水平包装方法

    公开(公告)号：US20130095612A1

    公开(公告)日：2013-04-18

    申请号：US13273168

    申请日：2011-10-13

    申请人： Ping Huang ,  Ruisheng Wu ,  Lei Duan ,  Yi Chen ,  Yuping Gong

    发明人： Ping Huang ,  Ruisheng Wu ,  Lei Duan ,  Yi Chen ,  Yuping Gong

    IPC分类号： H01L21/82

    CPC分类号： H01L23/3171 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/12105 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

    摘要： A chip-scale packaging method, with bottom and side of a semiconductor chip encapsulated, includes the following steps: attaching backside of a thinned semiconductor wafer to a dicing tape; separating individual chips by cutting from front side of the wafer at scribe line but not cut through the dicing tape; flipping and attaching the wafer onto a top surface of a double-sided tape, then removing the dicing tape; attaching bottom surface of the double-sided tape on a supporting plate; filling the space between adjacent chips and covering the whole wafer backside with a molding material; flipping the whole structure and remove the supporting plate; placing solder balls at corresponding positions on electrodes of each chip and performing backflow treatment; finally separating individual chip packages by cutting through molding material at the space between adjacent chip packages with molding material encapsulating the bottom and side of each individual semiconductor chip.

    摘要翻译： 封装了半导体芯片的底部和侧面的芯片级封装方法包括以下步骤：将薄化的半导体晶片的背面安装到切割带上; 通过在切割线处切割晶片的正面而不切割切割带来分离各个芯片; 翻转并将晶片连接到双面胶带的顶表面上，然后移除切割胶带; 将双面胶带的底面附着在支撑板上; 填充相邻芯片之间的空间并用模制材料覆盖整个晶片背面; 翻转整个结构并拆下支撑板; 将焊球放置在每个芯片的电极上的相应位置，并执行回流处理; 最后通过在封装每个单独的半导体芯片的底部和侧面的成型材料之间切割相邻芯片封装之间的空间处的模制材料来分离单个芯片封装。

    Wafer level chip scale package and method of laser marking the same
    8.
    发明授权
    Wafer level chip scale package and method of laser marking the same 有权
    晶圆级芯片级封装和激光打标方法相同

    公开(公告)号：US07842543B2

    公开(公告)日：2010-11-30

    申请号：US12378713

    申请日：2009-02-17

    申请人： Ruisheng Wu ,  Yan Liu ,  Tao Feng

    发明人： Ruisheng Wu ,  Yan Liu ,  Tao Feng

    IPC分类号： H01L21/50

    CPC分类号： H01L23/544 ,  H01L21/67282 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/274 ,  H01L2924/01079 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/13091

    摘要： A wafer level chip scale package and method of laser marking the same are disclosed. The method includes forming a plurality of semiconductor devices on a frontside surface of a wafer, metallizing device contacts on the frontside surface of the wafer, grinding the backside surface of the wafer, silicon etching the backside surface of the wafer, laser marking the backside surface of the wafer following the silicon etch step, oxide etching the backside surface of the wafer following the laser marking step, depositing a metal layer on the backside surface of the wafer following the oxide etch step, and dicing the wafer into wafer level chip scale packages. A wafer level chip scale package includes a mark formed on a backside surface thereof, the mark comprising a plurality of trenches formed in a silicon backside surface and corresponding indentations formed in an overlaying back metal layer.

    摘要翻译： 公开了一种晶片级芯片级封装及其激光标记方法。 该方法包括在晶片的前表面上形成多个半导体器件，金属化器件接触晶片的前侧表面，研磨晶片的背面，硅蚀刻晶片的背面，激光标记背面 在所述硅蚀刻步骤之后的所述晶片的氧化物，在所述激光标记步骤之后，氧化物蚀刻所述晶片的所述背面，在所述氧化物蚀刻步骤之后，在所述晶片的所述背面表面上沉积金属层，以及将所述晶片切割成晶片级芯片级封装 。 晶片级芯片级封装包括在其背面形成的标记，该标记包括形成在硅背面中的多个沟槽和形成在覆盖背面金属层中的相应凹痕。

    Wafer level chip scale package and method of laser marking the same
    9.
    发明申请
    Wafer level chip scale package and method of laser marking the same 有权
    晶圆级芯片级封装和激光打标方法相同

    公开(公告)号：US20100207283A1

    公开(公告)日：2010-08-19

    申请号：US12378713

    申请日：2009-02-17

    申请人： Ruisheng Wu ,  Yan Liu ,  Tao Feng

    发明人： Ruisheng Wu ,  Yan Liu ,  Tao Feng

    IPC分类号： H01L21/304 ,  H01L23/544

    CPC分类号： H01L23/544 ,  H01L21/67282 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/274 ,  H01L2924/01079 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/13091

    摘要： A wafer level chip scale package and method of laser marking the same are disclosed. The method includes forming a plurality of semiconductor devices on a frontside surface of a wafer, metallizing device contacts on the frontside surface of the wafer, grinding the backside surface of the wafer, silicon etching the backside surface of the wafer, laser marking the backside surface of the wafer following the silicon etch step, oxide etching the backside surface of the wafer following the laser marking step, depositing a metal layer on the backside surface of the wafer following the oxide etch step, and dicing the wafer into wafer level chip scale packages. A wafer level chip scale package includes a mark formed on a backside surface thereof, the mark comprising a plurality of trenches formed in a silicon backside surface and corresponding indentations formed in an overlaying back metal layer

    摘要翻译： 公开了一种晶片级芯片级封装及其激光标记方法。 该方法包括在晶片的前表面上形成多个半导体器件，金属化器件接触晶片的前侧表面，研磨晶片的背面，硅蚀刻晶片的背面，激光标记背面 在所述硅蚀刻步骤之后的所述晶片的氧化物，在所述激光标记步骤之后，氧化物蚀刻所述晶片的所述背面，在所述氧化物蚀刻步骤之后，在所述晶片的所述背面表面上沉积金属层，以及将所述晶片切割成晶片级芯片级封装 。 晶片级芯片级封装包括在其背面形成的标记，标记包括形成在硅背面中的多个沟槽和形成在覆盖背面金属层中的相应凹痕