公开(公告)号：US08241952B2

公开(公告)日：2012-08-14

申请号：US12713018

申请日：2010-02-25

申请人： Yaojian Lin ,  Robert C. Frye ,  Pandi Chelvam Marimuthu ,  Kai Liu

发明人： Yaojian Lin ,  Robert C. Frye ,  Pandi Chelvam Marimuthu ,  Kai Liu

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/49816 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14163 ,  H01L2224/14165 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive layer. A first insulating layer is formed over the die and resistive layer. The wafer is singulated to separate the die. The die is mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. The carrier and a portion of the encapsulant and first insulating layer is removed. A second insulating layer is formed over the encapsulant and first insulating layer. A second conductive layer is formed over the first and second insulating layers. A third insulating layer is formed over the second insulating layer and second conductive layer. A third conductive layer is formed over the third insulating layer and second conductive layer. A fourth insulating layer is formed over the third insulating layer and third conductive layer.

摘要翻译： 半导体晶片包含半导体晶片。 在模具上形成第一导电层。 在管芯和第一导电层上形成电阻层。 在管芯和电阻层上形成第一绝缘层。 将晶片单片化以分离模具。 模具安装到临时托架上。 密封剂沉积在模具和载体上。 移除载体和密封剂和第一绝缘层的一部分。 在密封剂和第一绝缘层之上形成第二绝缘层。 在第一绝缘层和第二绝缘层上形成第二导电层。 在第二绝缘层和第二导电层上形成第三绝缘层。 在第三绝缘层和第二导电层上形成第三导电层。 在第三绝缘层和第三导电层上形成第四绝缘层。

公开(公告)号：US20100001268A1

公开(公告)日：2010-01-07

申请号：US12167039

申请日：2008-07-02

申请人： Robert C. Frye ,  Kai Liu ,  Yaojian Lin

发明人： Robert C. Frye ,  Kai Liu ,  Yaojian Lin

IPC分类号： H01L23/58 ,  H01L21/02

CPC分类号： H01L22/34 ,  H01L23/64 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/3011 ,  H01L2924/00014

摘要： A semiconductor device has an inductor and capacitor formed on the substrate. The inductor and capacitor are electrically connected in series. The inductor is a coiled conductive layer. The capacitor has first and second conductive layers separated by an insulating layer. A first test pad and second test pad are formed on the substrate. A terminal of the inductor is coupled to the first and second test pads. A third test pad and fourth test pad are formed on the substrate. A terminal of the capacitor is coupled to the third and fourth test pads such that the inductor and capacitor are connected in shunt between the first and second test pads and the third and fourth test pads. An electrical characteristic of the inductor and capacitor such that resonant frequency and quality factor are tested using a two-port shunt measurement which negates series resistance of test probes.

摘要翻译： 半导体器件具有形成在衬底上的电感器和电容器。 电感器和电容器串联电连接。 电感器是线圈导电层。 该电容器具有被绝缘层隔开的第一和第二导电层。 在基板上形成第一测试焊盘和第二测试焊盘。 电感器的端子耦合到第一和第二测试焊盘。 在基板上形成第三测试焊盘和第四测试焊盘。 电容器的端子耦合到第三和第四测试焊盘，使得电感器和电容器在第一和第二测试焊盘与第三和第四测试焊盘之间分流连接。 电感器和电容器的电气特性使得谐振频率和品质因数使用双端口分流测量进行测试，这样可以消除测试探针的串联电阻。

公开(公告)号：US20120267800A1

公开(公告)日：2012-10-25

申请号：US13543088

申请日：2012-07-06

申请人： Yaojian Lin ,  Robert C. Frye ,  Pandi Chelvam Marimuthu ,  Kai Liu

发明人： Yaojian Lin ,  Robert C. Frye ,  Pandi Chelvam Marimuthu ,  Kai Liu

IPC分类号： H01L25/16 ,  H01L23/522

CPC分类号： H01L23/49816 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14163 ,  H01L2224/14165 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive layer. A first insulating layer is formed over the die and resistive layer. The wafer is singulated to separate the die. The die is mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. The carrier and a portion of the encapsulant and first insulating layer is removed. A second insulating layer is formed over the encapsulant and first insulating layer. A second conductive layer is formed over the first and second insulating layers. A third insulating layer is formed over the second insulating layer and second conductive layer. A third conductive layer is formed over the third insulating layer and second conductive layer. A fourth insulating layer is formed over the third insulating layer and third conductive layer.

摘要翻译： 半导体晶片包含半导体晶片。 在模具上形成第一导电层。 在管芯和第一导电层上形成电阻层。 在管芯和电阻层上形成第一绝缘层。 将晶片单片化以分离模具。 模具安装到临时托架上。 密封剂沉积在模具和载体上。 移除载体和密封剂和第一绝缘层的一部分。 在密封剂和第一绝缘层之上形成第二绝缘层。 在第一绝缘层和第二绝缘层上形成第二导电层。 在第二绝缘层和第二导电层上形成第三绝缘层。 在第三绝缘层和第二导电层上形成第三导电层。 在第三绝缘层和第三导电层上形成第四绝缘层。

公开(公告)号：US07906839B2

公开(公告)日：2011-03-15

申请号：US12167039

申请日：2008-07-02

申请人： Robert C. Frye ,  Kai Liu ,  Yaojian Lin

发明人： Robert C. Frye ,  Kai Liu ,  Yaojian Lin

IPC分类号： H01L23/02

CPC分类号： H01L22/34 ,  H01L23/64 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/3011 ,  H01L2924/00014

摘要： A semiconductor device has an inductor and capacitor formed on the substrate. The inductor and capacitor are electrically connected in series. The inductor is a coiled conductive layer. The capacitor has first and second conductive layers separated by an insulating layer. A first test pad and second test pad are formed on the substrate. A terminal of the inductor is coupled to the first and second test pads. A third test pad and fourth test pad are formed on the substrate. A terminal of the capacitor is coupled to the third and fourth test pads such that the inductor and capacitor are connected in shunt between the first and second test pads and the third and fourth test pads. An electrical characteristic of the inductor and capacitor such that resonant frequency and quality factor are tested using a two-port shunt measurement which negates series resistance of test probes.

摘要翻译： 半导体器件具有形成在衬底上的电感器和电容器。 电感器和电容器串联电连接。 电感器是线圈导电层。 该电容器具有被绝缘层隔开的第一和第二导电层。 在基板上形成第一测试焊盘和第二测试焊盘。 电感器的端子耦合到第一和第二测试焊盘。 在基板上形成第三测试焊盘和第四测试焊盘。 电容器的端子耦合到第三和第四测试焊盘，使得电感器和电容器在第一和第二测试焊盘与第三和第四测试焊盘之间分流连接。 电感器和电容器的电气特性使得谐振频率和品质因数使用双端口分流测量进行测试，这样可以消除测试探针的串联电阻。

公开(公告)号：US20090167455A1

公开(公告)日：2009-07-02

申请号：US12331492

申请日：2008-12-10

申请人： Kai Liu ,  Robert C. Frye ,  Yaojian Lin

发明人： Kai Liu ,  Robert C. Frye ,  Yaojian Lin

IPC分类号： H03H7/01

CPC分类号： H03H7/422 ,  H01L28/10 ,  H03H7/09 ,  H03H7/1766 ,  H03H7/42

摘要： A band-pass filter has a plurality of frequency band channels each including a first inductor having a first terminal coupled to a first balanced port and a second terminal coupled to a second balanced port. A first capacitor is coupled between the first and second terminals of the first inductor. A second inductor has a first terminal coupled to a first unbalanced port and a second terminal coupled to a second unbalanced port. The second inductor is disposed within a first distance of the first inductor to induce magnetic coupling. A second capacitor is coupled between the first and second terminals of the second inductor. A third inductor is disposed within a second distance of the first inductor and within a third distance of the second inductor to induce magnetic coupling. A second capacitor is coupled between first and second terminals of the third inductor.

摘要翻译： 带通滤波器具有多个频带信道，每个频带信道包括具有耦合到第一平衡端口的第一端子的第一电感器和耦合到第二平衡端口的第二端子。 第一电容器耦合在第一电感器的第一和第二端子之间。 第二电感器具有耦合到第一不平衡端口的第一端子和耦合到第二不平衡端口的第二端子。 第二电感器设置在第一电感器的第一距离内以引起磁耦合。 第二电容器耦合在第二电感器的第一和第二端子之间。 第三电感器设置在第一电感器的第二距离内并且在第二电感器的第三距离内，以引起磁耦合。 第二电容器耦合在第三电感器的第一和第二端子之间。

公开(公告)号：US08576026B2

公开(公告)日：2013-11-05

申请号：US12331492

申请日：2008-12-10

申请人： Kai Liu ,  Robert C. Frye ,  Yaojian Lin

发明人： Kai Liu ,  Robert C. Frye ,  Yaojian Lin

IPC分类号： H01P3/08 ,  H01P7/08

CPC分类号： H03H7/422 ,  H01L28/10 ,  H03H7/09 ,  H03H7/1766 ,  H03H7/42

摘要： A band-pass filter has a plurality of frequency band channels each including a first inductor having a first terminal coupled to a first balanced port and a second terminal coupled to a second balanced port. A first capacitor is coupled between the first and second terminals of the first inductor. A second inductor has a first terminal coupled to a first unbalanced port and a second terminal coupled to a second unbalanced port. The second inductor is disposed within a first distance of the first inductor to induce magnetic coupling. A second capacitor is coupled between the first and second terminals of the second inductor. A third inductor is disposed within a second distance of the first inductor and within a third distance of the second inductor to induce magnetic coupling. A second capacitor is coupled between first and second terminals of the third inductor.

摘要翻译： 带通滤波器具有多个频带信道，每个频带信道包括具有耦合到第一平衡端口的第一端子的第一电感器和耦合到第二平衡端口的第二端子。 第一电容器耦合在第一电感器的第一和第二端子之间。 第二电感器具有耦合到第一不平衡端口的第一端子和耦合到第二不平衡端口的第二端子。 第二电感器设置在第一电感器的第一距离内以引起磁耦合。 第二电容器耦合在第二电感器的第一和第二端子之间。 第三电感器设置在第一电感器的第二距离内并且在第二电感器的第三距离内，以引起磁耦合。 第二电容器耦合在第三电感器的第一和第二端子之间。

公开(公告)号：US09343396B2

公开(公告)日：2016-05-17

申请号：US13543088

申请日：2012-07-06

申请人： Yaojian Lin ,  Robert C. Frye ,  Pandi Chelvam Marimuthu ,  Kai Liu

发明人： Yaojian Lin ,  Robert C. Frye ,  Pandi Chelvam Marimuthu ,  Kai Liu

IPC分类号： H01L25/16 ,  H01L23/552 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00

CPC分类号： H01L23/49816 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14163 ,  H01L2224/14165 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive layer. A first insulating layer is formed over the die and resistive layer. The wafer is singulated to separate the die. The die is mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. The carrier and a portion of the encapsulant and first insulating layer is removed. A second insulating layer is formed over the encapsulant and first insulating layer. A second conductive layer is formed over the first and second insulating layers. A third insulating layer is formed over the second insulating layer and second conductive layer. A third conductive layer is formed over the third insulating layer and second conductive layer. A fourth insulating layer is formed over the third insulating layer and third conductive layer.

摘要翻译： 半导体晶片包含半导体晶片。 在模具上形成第一导电层。 在管芯和第一导电层上形成电阻层。 在管芯和电阻层上形成第一绝缘层。 将晶片单片化以分离模具。 模具安装到临时托架上。 密封剂沉积在模具和载体上。 移除载体和密封剂和第一绝缘层的一部分。 在密封剂和第一绝缘层之上形成第二绝缘层。 在第一绝缘层和第二绝缘层上形成第二导电层。 在第二绝缘层和第二导电层上形成第三绝缘层。 在第三绝缘层和第二导电层上形成第三导电层。 在第三绝缘层和第三导电层上形成第四绝缘层。

公开(公告)号：US20110204509A1

公开(公告)日：2011-08-25

申请号：US12713018

申请日：2010-02-25

申请人： Yaojian Lin ,  Robert C. Frye ,  Pandi Chelvam Marimuthu ,  Kai Liu

发明人： Yaojian Lin ,  Robert C. Frye ,  Pandi Chelvam Marimuthu ,  Kai Liu

IPC分类号： H01L23/48 ,  H01L21/78 ,  H01L21/50

CPC分类号： H01L23/49816 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14163 ,  H01L2224/14165 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive layer. A first insulating layer is formed over the die and resistive layer. The wafer is singulated to separate the die. The die is mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. The carrier and a portion of the encapsulant and first insulating layer is removed. A second insulating layer is formed over the encapsulant and first insulating layer. A second conductive layer is formed over the first and second insulating layers. A third insulating layer is formed over the second insulating layer and second conductive layer. A third conductive layer is formed over the third insulating layer and second conductive layer. A fourth insulating layer is formed over the third insulating layer and third conductive layer.

摘要翻译： 半导体晶片包含半导体晶片。 在模具上形成第一导电层。 在管芯和第一导电层上形成电阻层。 在管芯和电阻层上形成第一绝缘层。 将晶片单片化以分离模具。 模具安装到临时托架上。 密封剂沉积在模具和载体上。 移除载体和密封剂和第一绝缘层的一部分。 在密封剂和第一绝缘层之上形成第二绝缘层。 在第一绝缘层和第二绝缘层上形成第二导电层。 在第二绝缘层和第二导电层上形成第三绝缘层。 在第三绝缘层和第二导电层上形成第三导电层。 在第三绝缘层和第三导电层上形成第四绝缘层。

公开(公告)号：US08502339B2

公开(公告)日：2013-08-06

申请号：US12813315

申请日：2010-06-10

申请人： Yaojian Lin ,  Robert C. Frye

发明人： Yaojian Lin ,  Robert C. Frye

IPC分类号： H01L21/02

CPC分类号： H01L23/52 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/64 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/16 ,  H05K3/20 ,  H05K3/284 ,  H05K3/4644 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding.

公开(公告)号：US08399990B2

公开(公告)日：2013-03-19

申请号：US13355354

申请日：2012-01-20

申请人： Yaojian Lin ,  Robert C. Frye

发明人： Yaojian Lin ,  Robert C. Frye

IPC分类号： H01L23/48

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105

摘要： A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.

摘要翻译： 一种制造半导体器件的方法包括提供具有设置在基板的顶表面上的第一导电层的基板。 在基板和第一导电层上形成高电阻率层。 介电层沉积在衬底，第一导电层和高电阻率层上。 介电层，高电阻率层和第一导电层的一部分形成电容器叠层。 在电介质层上形成第一钝化层。 在电容器堆叠和第一钝化层的一部分上形成第二导电层。 在电介质层中蚀刻第一开口以暴露高电阻率层的表面。 在电介质层中的第一开口和第一钝化层的一部分上沉积第三和第四导电层。