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    Method of limiting sticking of body to susceptor in a deposition treatment
    1.
    发明授权
    Method of limiting sticking of body to susceptor in a deposition treatment 失效
    在沉积处理中限制身体对感受器的粘附的方法

    公开(公告)号：US5380566A

    公开(公告)日：1995-01-10

    申请号：US080018

    申请日：1993-06-21

    申请人： Robert Robertson ,  Marc M. Kollrack ,  Angela T. Lee ,  Kam Law ,  Dan Maydan

    发明人： Robert Robertson ,  Marc M. Kollrack ,  Angela T. Lee ,  Kam Law ,  Dan Maydan

    IPC分类号： C23C16/50 ,  C23C16/509 ,  C23C16/56 ,  B05D3/06

    CPC分类号： C23C16/56 ,  C23C16/509

    摘要： A method of limiting sticking of a body (substrate) to a susceptor after the body has been coated with a layer in a deposition chamber by plasma chemical vapor deposition includes subjecting the coated body to a plasma of an inactive gas, e.g., hydrogen, nitrogen, argon or ammonia, which does not adversely affect the coating and does not add additional layers to the body. After the coated body is subjected to the plasma of the inactive gas, the body is separated from the susceptor.

    摘要翻译： 在通过等离子体化学气相沉积在体积已经在沉积室中涂覆了层之后，将体（衬底）粘附到基座上的方法包括使涂覆体经受惰性气体例如氢气，氮气等离子体 ，氩或氨，其不会对涂层产生不利影响，并且不向身体添加额外的层。 在涂覆体经受惰性气体的等离子体之后，主体与基座分离。

    Multi-step chemical vapor deposition method for thin film transistors
    3.
    发明授权
    Multi-step chemical vapor deposition method for thin film transistors 失效
    薄膜晶体管的多步骤化学气相沉积方法

    公开(公告)号：US5441768A

    公开(公告)日：1995-08-15

    申请号：US193310

    申请日：1994-02-08

    申请人： Kam S. Law ,  Robert Robertson ,  Michael Kollrack ,  Angela T. Lee ,  Takako Takehara ,  Guofu J. Feng ,  Dan Maydan

    发明人： Kam S. Law ,  Robert Robertson ,  Michael Kollrack ,  Angela T. Lee ,  Takako Takehara ,  Guofu J. Feng ,  Dan Maydan

    IPC分类号： H01L21/205 ,  C23C16/24 ,  C23C16/34 ,  H01L21/31 ,  H01L21/318 ,  H01L21/336 ,  H01L29/786 ,  C23C16/22

    CPC分类号： H01L29/66765 ,  C23C16/24 ,  C23C16/345

    摘要： An improved method of depositing films of a gate silicon nitride and an amorphous silicon on a thin film transistor substrate at high deposition rates while maintaining superior film quality is provided. The material near the interface between the amorphous silicon and the nitride are deposited at a low deposition rate which produces superior quality films. The region away from the interface are deposited at a high deposition rate which produces lesser, but still good quality films. By using this method, superior quality thin film transistors can be produced at very high efficiency. The method can be carried out by depositing a high quality g-SiN.sub.x at a low deposition rate on top of an average quality gate nitride deposited at a high deposition rate and then depositing an amorphous silicon layer. It also applies in a process where high quality amorphous silicon is first deposited at a low deposition rate on a gate nitride layer to form an interface, and then average quality amorphous silicon is deposited at a high deposition rate to complete the silicon layer. The unique process can be applied whenever an interface exists with an active semiconductor layer of amorphous silicon. The process is applicable to either the back channel etched TFT device or the etch stopped TFT device.

    摘要翻译： 提供了一种在保持优异的膜质量的同时以高沉积速率在薄膜晶体管基板上沉积栅极氮化硅和非晶硅的膜的改进方法。 在非晶硅和氮化物之间的界面附近的材料以低沉积速率沉积，其产生优质的膜。 离开界面的区域以高沉积速率沉积，其产生较小但仍然是优质的膜。 通过使用该方法，能够以非常高的效率制造出优质的薄膜晶体管。 该方法可以通过在以高沉积速率沉积的平均质量的氮化镓的顶部上以低沉积速率沉积高质量的g-SiNx，然后沉积非晶硅层来进行。 它也适用于首先在栅极氮化物层上以低沉积速率沉积高品质非晶硅以形成界面的过程，然后以高沉积速率淀积平均质量的非晶硅以完成硅层。 每当与非晶硅的有源半导体层存在界面时，可以应用独特的工艺。 该工艺适用于后沟道蚀刻TFT器件或蚀刻停止的TFT器件。

    Multi-step chemical vapor deposition method for thin film transistors
    4.
    发明授权
    Multi-step chemical vapor deposition method for thin film transistors 失效
    薄膜晶体管的多步骤化学气相沉积方法

    公开(公告)号：US5567476A

    公开(公告)日：1996-10-22

    申请号：US427772

    申请日：1995-04-25

    申请人： Kam S. Law ,  Robert Robertson ,  Michael Kollrack ,  Angela T. Lee ,  Takako Takehara ,  Guofu J. Feng ,  Dan Maydan

    发明人： Kam S. Law ,  Robert Robertson ,  Michael Kollrack ,  Angela T. Lee ,  Takako Takehara ,  Guofu J. Feng ,  Dan Maydan

    IPC分类号： H01L21/205 ,  C23C16/24 ,  C23C16/34 ,  H01L21/31 ,  H01L21/318 ,  H01L21/336 ,  H01L29/786 ,  C23C16/00

    CPC分类号： H01L29/66765 ,  C23C16/24 ,  C23C16/345

    摘要： A multi-step CVD method for thin film transistor is disclosed. The method can be carried out by depositing a high quality g-SiN.sub.x at a low deposition rate on top of an average quality gate nitride deposited at a high deposition rate and then depositing an amorphous silicon layer. It also applies in a process where high quality amorphous silicon is first deposited at a low deposition rate on a gate nitride layer to form an interface, and then average quality amorphous silicon is deposited at a high deposition rate to complete the silicon layer. The unique process can be applied whenever an interface exists with an active semiconductor layer of amorphous silicon. The process is applicable to either the back channel etched TFT device or the etch stopped TFT device.

    摘要翻译： 公开了薄膜晶体管的多步CVD方法。 该方法可以通过在以高沉积速率沉积的平均质量的氮化镓的顶部上以低沉积速率沉积高质量的g-SiNx，然后沉积非晶硅层来进行。 它也适用于首先在栅极氮化物层上以低沉积速率沉积高品质非晶硅以形成界面的过程，然后以高沉积速率淀积平均质量的非晶硅以完成硅层。 每当与非晶硅的有源半导体层存在界面时，可以应用独特的工艺。 该工艺适用于后沟道蚀刻TFT器件或蚀刻停止的TFT器件。

    Single chamber CVD process for thin film transistors
    8.
    发明授权
    Single chamber CVD process for thin film transistors 失效
    用于薄膜晶体管的单室CVD工艺

    公开(公告)号：US5589233A

    公开(公告)日：1996-12-31

    申请号：US466915

    申请日：1995-06-06

    申请人： Kam Law ,  Robert Robertson ,  Guofu J. Feng

    发明人： Kam Law ,  Robert Robertson ,  Guofu J. Feng

    IPC分类号： C23C16/44 ,  H01L21/205 ,  H01L21/336 ,  H01L29/786 ,  C23C16/00 ,  B05D3/06

    CPC分类号： H01L29/66765 ,  C23C16/4404 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  Y10S438/905

    摘要： A method of depositing layers of intrinsic amorphous silicon and doped amorphous silicon sequentially on a substrate in the same CVD chamber without incurring a dopant contamination problem. The method can be carried out by first depositing an additional layer of a dielectric insulating material prior to the deposition process of the intrinsic amorphous silicon layer. The additional layer of insulating material deposited on the substrate should have a thickness such that residual insulating material coated on the chamber walls is sufficient to cover the residual dopants on the chamber walls left by the deposition process of the previous substrate. This provides a clean environment for the next deposition process of an intrinsic amorphous silicon layer on a substrate in the same CVD chamber.

    摘要翻译： 本征非晶硅和掺杂的非晶硅的顺序沉积在相同CVD室中的衬底上的方法，而不会引起掺杂剂污染问题。 该方法可以通过在本征非晶硅层的沉积工艺之前首先沉积介电绝缘材料的附加层来进行。 沉积在基板上的附加绝缘材料层应该具有使得涂覆在室壁上的残留绝缘材料足以覆盖由先前基板的沉积工艺留下的室壁上的残留掺杂剂的厚度。 这为在同一CVD室中的衬底上的本征非晶硅层的下一个沉积工艺提供了清洁的环境。