公开(公告)号：US08314484B2

公开(公告)日：2012-11-20

申请号：US12691175

申请日：2010-01-21

申请人： Ryoichi Kajiwara ,  Shigehisa Motowaki ,  Kazutoshi Ito ,  Toshiaki Ishii ,  Katsuo Arai ,  Takuya Nakajo ,  Hidemasa Kagii

发明人： Ryoichi Kajiwara ,  Shigehisa Motowaki ,  Kazutoshi Ito ,  Toshiaki Ishii ,  Katsuo Arai ,  Takuya Nakajo ,  Hidemasa Kagii

IPC分类号： H01L23/15

CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/04026 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/8392 ,  H01L2224/83951 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85447 ,  H01L2224/8592 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/05432 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01032 ,  H01L2924/3512 ,  H01L2224/48744

摘要： In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.

摘要翻译： 在半导体器件的结构中，Si芯片和金属引线框通过金属接合，通过具有三维网状结构的高导电性金属的多孔接合层，使用Ag作为接合材料，以及含有 在与聚合物树脂接触的半导体组件的表面上形成氧化锌或氧化铝。 以这种方式，通过与主要由Ag形成的多孔结构的接合层的接合，可以降低Si片的热应力负荷，并且可以提高接合层本身的疲劳寿命。 此外，由于通过锚固效应可以提高聚合物树脂对膜的粘附性，可以防止接合部发生裂纹，从而可以提供高可靠性的无铅半导体器件。

公开(公告)号：US20080220568A1

公开(公告)日：2008-09-11

申请号：US12117359

申请日：2008-05-08

申请人： Akira MUTO ,  Ichio Shimizu ,  Katsuo Arai ,  Hidemasa Kagii ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Takuya Nakajo ,  Keiichi Okawa ,  Masahiko Osaka

发明人： Akira MUTO ,  Ichio Shimizu ,  Katsuo Arai ,  Hidemasa Kagii ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Takuya Nakajo ,  Keiichi Okawa ,  Masahiko Osaka

IPC分类号： H01L23/28

CPC分类号： H01L23/49562 ,  H01L23/3107 ,  H01L23/49537 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/84 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a back surface of a sealing resin portion, a first portion of a drain terminal connected to a back-surface drain electrode of the semiconductor chip is exposed to an upper surface of the sealing resin portion, and a second portion of the drain terminal formed integrally with the first portion of the drain terminal is exposed to the back surface of the sealing resin portion. When forming the sealing resin portion in such a semiconductor device, first the sealing resin portion is formed so as to also cover an upper surface of the first portion of the drain terminal and thereafter the upper surface side of the sealing resin portion is polished by liquid honing, thereby allowing the upper surface of the first portion of the drain terminal to be exposed on the upper surface of the sealing resin portion. Both heat dissipating property and production yield of the semiconductor device are improved.

摘要翻译： 公开了一种树脂密封半导体封装形式的半导体器件，其中连接到形成在半导体芯片的表面上的栅极焊盘电极的栅极端子和连接到形成在芯片表面上的源极焊盘电极的源极端子暴露于 密封树脂部分的背面，连接到半导体芯片的背面漏电极的漏极端子的第一部分暴露于密封树脂部分的上表面，并且漏极端子的第二部分整体地形成 漏极端子的第一部分暴露于密封树脂部分的背面。 当在这种半导体器件中形成密封树脂部分时，首先形成密封树脂部分，以便也覆盖漏极端子的第一部分的上表面，此后密封树脂部分的上表面侧被液体 从而允许排水端子的第一部分的上表面暴露在密封树脂部分的上表面上。 改善了半导体器件的散热性能和生产成本。

公开(公告)号：US07374965B2

公开(公告)日：2008-05-20

申请号：US11348362

申请日：2006-02-07

申请人： Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hidemasa Kagii ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Takuya Nakajo ,  Keiichi Okawa ,  Masahiko Osaka

发明人： Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hidemasa Kagii ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Takuya Nakajo ,  Keiichi Okawa ,  Masahiko Osaka

IPC分类号： H01L21/00

CPC分类号： H01L23/49562 ,  H01L23/3107 ,  H01L23/49537 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/84 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a back surface of a sealing resin portion, a first portion of a drain terminal connected to a back-surface drain electrode of the semiconductor chip is exposed to an upper surface of the sealing resin portion, and a second portion of the drain terminal formed integrally with the first portion of the drain terminal is exposed to the back surface of the sealing resin portion. When forming the sealing resin portion in such a semiconductor device, first the sealing resin portion is formed so as to also cover an upper surface of the first portion of the drain terminal and thereafter the upper surface side of the sealing resin portion is polished by liquid honing, thereby allowing the upper surface of the first portion of the drain terminal to be exposed on the upper surface of the sealing resin portion. Both heat dissipating property and production yield of the semiconductor device are improved.

摘要翻译： 公开了一种树脂密封半导体封装形式的半导体器件，其中连接到形成在半导体芯片的表面上的栅极焊盘电极的栅极端子和连接到形成在芯片表面上的源极焊盘电极的源极端子暴露于 密封树脂部分的背面，连接到半导体芯片的背面漏电极的漏极端子的第一部分暴露于密封树脂部分的上表面，并且漏极端子的第二部分整体地形成 漏极端子的第一部分暴露于密封树脂部分的背面。 当在这种半导体器件中形成密封树脂部分时，首先形成密封树脂部分，以便也覆盖漏极端子的第一部分的上表面，此后密封树脂部分的上表面侧被液体 从而允许排水端子的第一部分的上表面暴露在密封树脂部分的上表面上。 改善了半导体器件的散热性能和生产成本。

公开(公告)号：US07220617B2

公开(公告)日：2007-05-22

申请号：US11349219

申请日：2006-02-08

申请人： Hidemasa Kagii ,  Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Masahiko Osaka ,  Takuya Nakajo ,  Keiichi Okawa ,  Hiroi Oka

发明人： Hidemasa Kagii ,  Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Masahiko Osaka ,  Takuya Nakajo ,  Keiichi Okawa ,  Hiroi Oka

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L23/24 ,  H01L21/52 ,  H01L23/488 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/40225 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals being exposed. Mounting surfaces of the metal plate terminals and a third part of the metal cap are bonded to electrodes on a mounting board.

摘要翻译： 半导体芯片由树脂密封而不覆盖具有功率晶体管的半导体器件的外部端子。 具有功率晶体管的半导体芯片容纳在金属盖的凹部内，而半导体芯片的第一表面上的漏电极经由连接材料接合到凹部的底部。 在与半导体芯片的第一表面相对的第二表面上形成栅电极和源电极，并且栅极电极和源极电极与金属板端子接合。 此外，半导体芯片被树脂密封体密封，金属板端子的安装表面露出。 金属板端子和金属盖的第三部分的安装表面与安装板上的电极接合。

公开(公告)号：US20060175700A1

公开(公告)日：2006-08-10

申请号：US11349219

申请日：2006-02-08

申请人： Hidemasa Kagii ,  Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Masahiko Osaka ,  Takuya Nakajo ,  Keiichi Okawa ,  Hiroi Oka

发明人： Hidemasa Kagii ,  Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Masahiko Osaka ,  Takuya Nakajo ,  Keiichi Okawa ,  Hiroi Oka

IPC分类号： H01L23/34

CPC分类号： H01L23/24 ,  H01L21/52 ,  H01L23/488 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/40225 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals being exposed. Mounting surfaces of the metal plate terminals and a third part of the metal cap are bonded to electrodes on a mounting board.

摘要翻译： 半导体芯片由树脂密封而不覆盖具有功率晶体管的半导体器件的外部端子。 具有功率晶体管的半导体芯片容纳在金属盖的凹部内，而半导体芯片的第一表面上的漏电极经由连接材料接合到凹部的底部。 在与半导体芯片的第一表面相对的第二表面上形成栅极电极和源极电极，并且栅极电极和源极电极与金属板端子接合。此外，半导体芯片由树脂密封体 金属板端子的安装表面露出。 金属板端子和金属盖的第三部分的安装表面与安装板上的电极接合。

公开(公告)号：US20080268577A1

公开(公告)日：2008-10-30

申请号：US12164625

申请日：2008-06-30

申请人： Hidemasa KAGII ,  Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Masahiko Osaka ,  Takuya Nakajo ,  Keiichi Okawa ,  Hiroi Oka

发明人： Hidemasa KAGII ,  Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Masahiko Osaka ,  Takuya Nakajo ,  Keiichi Okawa ,  Hiroi Oka

IPC分类号： H01L21/00

CPC分类号： H01L23/24 ,  H01L21/52 ,  H01L23/488 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/40225 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6G, 6S via connection materials 5b, 5c. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6G, 6S being exposed. Mounting surfaces of the metal plate terminals 6G, 6S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5e, 5f and 5g.

摘要翻译： 半导体芯片由树脂密封而不覆盖具有功率晶体管的半导体器件的外部端子。 具有功率晶体管的半导体芯片容纳在金属盖的凹部内，而半导体芯片的第一表面上的漏电极经由连接材料接合到凹部的底部。 在与半导体芯片的第一表面相对的第二表面上形成栅电极和源电极，并且栅电极和源电极通过连接材料5b，5c连接金属板端子6G，6S 。 此外，半导体芯片由金属板端子6G，6S的露出的安装面的树脂密封体密封。 金属板端子6G，6S和金属盖的第三部分的安装表面通过连接材料5e，5f和5g与安装板10上的电极接合。

公开(公告)号：US07405469B2

公开(公告)日：2008-07-29

申请号：US11783919

申请日：2007-04-13

申请人： Hidemasa Kagii ,  Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Masahiko Osaka ,  Takuya Nakajo ,  Keiichi Okawa ,  Hiroi Oka

发明人： Hidemasa Kagii ,  Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Masahiko Osaka ,  Takuya Nakajo ,  Keiichi Okawa ,  Hiroi Oka

IPC分类号： H01L23/495

CPC分类号： H01L23/24 ,  H01L21/52 ,  H01L23/488 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/40225 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6G, 6S via connection materials 5b, 5c. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6G, 6S being exposed. Mounting surfaces of the metal plate terminals 6G, 6S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5e, 5f and 5g.

摘要翻译： 半导体芯片由树脂密封而不覆盖具有功率晶体管的半导体器件的外部端子。 具有功率晶体管的半导体芯片容纳在金属盖的凹部内，而半导体芯片的第一表面上的漏电极经由连接材料接合到凹部的底部。 在与半导体芯片的第一表面相对的第二表面上形成栅电极和源电极，并且栅电极和源电极通过连接材料5b，5c连接金属板端子6G，6S 。 此外，半导体芯片由金属板端子6G，6S的露出的安装面的树脂密封体密封。 金属板端子6G，6S和金属盖的第三部分的安装表面通过连接材料5e，5f和5g与安装板10上的电极接合。

公开(公告)号：US20060177967A1

公开(公告)日：2006-08-10

申请号：US11348362

申请日：2006-02-07

申请人： Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hidemasa Kagii ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Takuya Nakajo ,  Keiichi Okawa ,  Masahiko Osaka

发明人： Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hidemasa Kagii ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Takuya Nakajo ,  Keiichi Okawa ,  Masahiko Osaka

IPC分类号： H01L21/50

CPC分类号： H01L23/49562 ,  H01L23/3107 ,  H01L23/49537 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/84 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a back surface of a sealing resin portion, a first portion of a drain terminal connected to a back-surface drain electrode of the semiconductor chip is exposed to an upper surface of the sealing resin portion, and a second portion of the drain terminal formed integrally with the first portion of the drain terminal is exposed to the back surface of the sealing resin portion. When forming the sealing resin portion in such a semiconductor device, first the sealing resin portion is formed so as to also cover an upper surface of the first portion of the drain terminal and thereafter the upper surface side of the sealing resin portion is polished by liquid honing, thereby allowing the upper surface of the first portion of the drain terminal to be exposed on the upper surface of the sealing resin portion. Both heat dissipating property and production yield of the semiconductor device are improved.

摘要翻译： 公开了一种树脂密封半导体封装形式的半导体器件，其中连接到形成在半导体芯片的表面上的栅极焊盘电极的栅极端子和连接到形成在芯片表面上的源极焊盘电极的源极端子暴露于 密封树脂部分的背面，连接到半导体芯片的背面漏电极的漏极端子的第一部分暴露于密封树脂部分的上表面，并且漏极端子的第二部分整体地形成 漏极端子的第一部分暴露于密封树脂部分的背面。 当在这种半导体器件中形成密封树脂部分时，首先形成密封树脂部分，以便也覆盖漏极端子的第一部分的上表面，此后密封树脂部分的上表面侧被液体 从而允许排水端子的第一部分的上表面暴露在密封树脂部分的上表面上。 改善了半导体器件的散热性能和生产成本。

公开(公告)号：US20070210430A1

公开(公告)日：2007-09-13

申请号：US11783919

申请日：2007-04-13

申请人： Hidemasa Kagii ,  Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Masahiko Osaka ,  Takuya Nakajo ,  Keiichi Okawa ,  Hiroi Oka

发明人： Hidemasa Kagii ,  Akira Muto ,  Ichio Shimizu ,  Katsuo Arai ,  Hiroshi Sato ,  Hiroyuki Nakamura ,  Masahiko Osaka ,  Takuya Nakajo ,  Keiichi Okawa ,  Hiroi Oka

IPC分类号： H01L23/02

CPC分类号： H01L23/24 ,  H01L21/52 ,  H01L23/488 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/40225 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6G, 6S via connection materials 5b, 5c. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6G, 6S being exposed. Mounting surfaces of the metal plate terminals 6G, 6S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5e, 5f and 5g.

摘要翻译： 半导体芯片由树脂密封而不覆盖具有功率晶体管的半导体器件的外部端子。 具有功率晶体管的半导体芯片容纳在金属盖的凹部内，而半导体芯片的第一表面上的漏电极经由连接材料接合到凹部的底部。 在与半导体芯片的第一表面相对的第二表面上形成栅电极和源电极，并且栅电极和源电极通过连接材料5b，5c连接金属板端子6G，6S 。 此外，半导体芯片由金属板端子6G，6S的露出的安装面的树脂密封体密封。 金属板端子6G，6S和金属盖的第三部分的安装表面通过连接材料5e，5f和5g与安装板10上的电极接合。

公开(公告)号：US5304512A

公开(公告)日：1994-04-19

申请号：US994888

申请日：1992-12-22

申请人： Katsuo Arai ,  Sumio Okada ,  Takashi Ooba ,  Kazuya Takahashi ,  Mayumi Kaneko

发明人： Katsuo Arai ,  Sumio Okada ,  Takashi Ooba ,  Kazuya Takahashi ,  Mayumi Kaneko

IPC分类号： H01L21/56 ,  H01L21/60

CPC分类号： H01L21/56 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/50 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  Y10T29/49121

摘要： A chip 12 having an electric circuit and a plurality of leads 8 connected electrically with the chip 12 are molded in a resin-sealed package 46 by a molding material containing a main component of a resin, by introducing a molding compound sheet 20 into the cavities 33 of molds 31, 32 before the molds are clamped, by melting the molding compound sheet 20 in the cavities 33 into a liquid molding material 45 after the mold clamping action to pressure fill up the inside of the cavities 33, and by setting the liquid molding material 45 integrally.

摘要翻译： 具有电路的芯片12和与芯片12电连接的多个引线8通过包含树脂的主要成分的模制材料在树脂密封封装46中模制，通过将模塑复合片20引入到模腔 在模具被夹紧之前，通过在模具夹紧动作之后将空腔33中的模塑复合材料片20熔化成液体模制材料45以将压力填满空腔33的内部，并且通过将液体 一体成型材料45。