公开(公告)号：US09281259B2

公开(公告)日：2016-03-08

申请号：US14079273

申请日：2013-11-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Jose Alvin Caparas ,  Glenn Omandam

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/315 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device.

Abstract translation: 半导体器件具有安装到载体上的半导体管芯。 第一密封剂沉积在半导体管芯和载体上。 加强支撑构件可以设置在半导体管芯周围的载体上。 在第一密封剂中形成多个通道或凹槽。 可以通过去除第一密封剂的一部分来形成凹部。 或者，凹部形成在具有多个延伸表面的追逐模具中。 可以将第二密封剂沉积到第一密封剂的凹部中。 移除载体并且在半导体管芯和第一密封剂上形成互连结构。 第一密封剂的厚度提供足够的刚度以减少翘曲，同时凹槽在形成互连结构期间提供应力释放。 去除第一密封剂和凹部的一部分以减小半导体器件的厚度。

公开(公告)号：US09054083B2

公开(公告)日：2015-06-09

申请号：US14143891

申请日：2013-12-30

Applicant: STATS ChipPAC, Ltd.

Inventor： Nathapong Suthiwongsunthorn ,  Pandi C. Marimuthu ,  Jae Hun Ku ,  Glenn Omandam ,  Hin Hwa Goh ,  Kock Liang Heng ,  Jose A. Caparas

IPC: H01L21/311 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.

Abstract translation: 半导体器件包括衬底和延伸通过衬底的通孔。 第一绝缘层设置在通孔的侧壁上。 在第一绝缘层上的通孔中设置导电材料以形成TSV。 第一互连结构设置在衬底的第一侧上。 半导体管芯或部件安装到第一互连结构。 密封剂设置在第一互连结构和半导体管芯或部件上。 第二互连结构设置在衬底的第二侧上。 第二互连结构电连接到TSV。 第二互连结构包括设置在衬底的第二表面上的第二绝缘层和TSV，以及设置在TSV上方并通过第二绝缘层与TSV接触的第一导电层。

公开(公告)号：US20140110861A1

公开(公告)日：2014-04-24

申请号：US14143891

申请日：2013-12-30

Applicant: STATS ChipPAC, Ltd

Inventor： Nathapong Suthiwongsunthorn ,  Pandi C. Marimuthu ,  Jae Hun Ku ,  Glenn Omandam ,  Hin Hwa Goh ,  Kock Liang Heng ,  Jose A. Caparas

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.

Abstract translation: 半导体器件包括衬底和延伸穿过衬底的通孔。 第一绝缘层设置在通孔的侧壁上。 在第一绝缘层上的通孔中设置导电材料以形成TSV。 第一互连结构设置在衬底的第一侧上。 半导体管芯或部件安装到第一互连结构。 密封剂设置在第一互连结构和半导体管芯或部件上。 第二互连结构设置在衬底的第二侧上。 第二互连结构电连接到TSV。 第二互连结构包括设置在衬底的第二表面上的第二绝缘层和TSV，以及设置在TSV上方并通过第二绝缘层与TSV接触的第一导电层。

公开(公告)号：US20140061944A1

公开(公告)日：2014-03-06

申请号：US14079273

申请日：2013-11-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Jose Alvin Caparas ,  Glenn Omandam

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L23/315 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device.

Abstract translation: 半导体器件具有安装到载体上的半导体管芯。 第一密封剂沉积在半导体管芯和载体上。 加强支撑构件可以设置在半导体管芯周围的载体上。 在第一密封剂中形成多个通道或凹槽。 可以通过去除第一密封剂的一部分来形成凹部。 或者，凹部形成在具有多个延伸表面的追逐模具中。 可以将第二密封剂沉积到第一密封剂的凹部中。 移除载体并且在半导体管芯和第一密封剂上形成互连结构。 第一密封剂的厚度提供足够的刚度以减少翘曲，同时凹槽在形成互连结构期间提供应力释放。 去除第一密封剂和凹部的一部分以减小半导体器件的厚度。