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    Semiconductor device and method of forming dual-sided interconnect structures in FO-WLCSP
    1.
    发明授权
    Semiconductor device and method of forming dual-sided interconnect structures in FO-WLCSP 有权

    公开(公告)号：US10192796B2

    公开(公告)日：2019-01-29

    申请号：US13832205

    申请日：2013-03-15

    Applicant: STATS ChipPAC, Ltd.

    Inventor： Yaojian Lin ,  Kang Chen

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/66 ,  H01L21/56 ,  H01L23/498 ,  H01L23/28 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L21/48 ,  H01L21/78 ,  H01L23/538

    Abstract: A semiconductor device has a substrate with first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the bumps. An encapsulant is deposited over the substrate and semiconductor die. A portion of the bumps extends out from the encapsulant. A portion of the encapsulant is removed to expose the substrate. An interconnect structure is formed over the encapsulant and semiconductor die and electrically coupled to the bumps. A portion of the substrate can be removed to expose the first or second conductive layer. A portion of the substrate can be removed to expose the bumps. The substrate can be removed and a protection layer formed over the encapsulant and semiconductor die. A semiconductor package is disposed over the substrate and electrically connected to the substrate.

    Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
    2.
    发明授权
    Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units 有权

    公开(公告)号：US10049964B2

    公开(公告)日：2018-08-14

    申请号：US14061244

    申请日：2013-10-23

    Applicant: STATS ChipPAC, Ltd.

    Inventor： Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Yu Gu

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538

    Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters.

    Semiconductor Device and Method of Forming Through Mold Hole with Alignment and Dimension Control
    9.
    发明申请
    Semiconductor Device and Method of Forming Through Mold Hole with Alignment and Dimension Control 有权
    半导体器件和通过对准和尺寸控制的模具孔形成的方法

    公开(公告)号：US20150028471A1

    公开(公告)日：2015-01-29

    申请号：US13950122

    申请日：2013-07-24

    Applicant: STATS ChipPAC, Ltd.

    Inventor： Yaojian Lin ,  Kang Chen ,  Yu Gu

    IPC: H01L23/498 ,  H01L21/66

    CPC classification number: H01L23/49811 ,  H01L22/12 ,  H01L22/20 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor die and an encapsulant formed over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A plurality of conductive vias is formed through the first insulating layer. A conductive pad is formed over the encapsulant. An interconnect structure is formed over the semiconductor die and encapsulant. A first opening is formed in the encapsulant to expose the conductive vias. The conductive vias form a conductive via array. The conductive via array is inspected through the first opening to measure a dimension of the first opening and determine a position of the first opening. The semiconductor device is adjusted based on a position of the conductive via array. A conductive material is formed in the first opening over the conductive via array.

    Abstract translation: 半导体器件包括形成在半导体管芯的第一表面上并围绕半导体管芯的半导体管芯和密封剂。 在半导体管芯的与第一表面相对的第二表面上形成第一绝缘层。 通过第一绝缘层形成多个导电孔。 在密封剂上形成导电焊盘。 在半导体管芯和密封剂上形成互连结构。 在密封剂中形成第一开口以暴露导电通孔。 导电通孔形成导电通孔阵列。 通过第一开口检查导电通孔阵列以测量第一开口的尺寸并确定第一开口的位置。 基于导电通孔阵列的位置来调整半导体器件。 在导电通孔阵列上的第一开口中形成导电材料。

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