公开(公告)号：US07656035B2

公开(公告)日：2010-02-02

申请号：US12351689

申请日：2009-01-09

申请人： Sairam Agraharam ,  Carlton Hanna ,  Dongming He ,  Vasudeva Atluri ,  Debendra Mallik ,  Matthew Escobido ,  Sujit Sharan

发明人： Sairam Agraharam ,  Carlton Hanna ,  Dongming He ,  Vasudeva Atluri ,  Debendra Mallik ,  Matthew Escobido ,  Sujit Sharan

IPC分类号： H01L23/485

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13017 ,  H01L2224/13099 ,  H01L2224/16058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05099

摘要： In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.

摘要翻译： 在一个实施例中，本发明提供了一种方法，其包括在管芯上制造管芯凸块，所述管芯凸块的形状和尺寸被设计成至少减小所使用的焊料材料的流动，以将管芯凸块附接到封装衬底 位于模具凸块下方的冶金（UBM）层。 有利地，该方法可以包括执行衬底回流操作以将封装衬底附接到管芯凸块，而不执行单独的晶片回流操作以回流管芯凸块。

公开(公告)号：US07517787B2

公开(公告)日：2009-04-14

申请号：US11087180

申请日：2005-03-22

申请人： Sairam Agraharam ,  Carlton Hanna ,  Dongming He ,  Vasudeva Atluri ,  Debendra Mallik ,  Matthew Escobido ,  Sujit Sharan

发明人： Sairam Agraharam ,  Carlton Hanna ,  Dongming He ,  Vasudeva Atluri ,  Debendra Mallik ,  Matthew Escobido ,  Sujit Sharan

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13017 ,  H01L2224/13099 ,  H01L2224/16058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05099

摘要： In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.

摘要翻译： 在一个实施例中，本发明提供了一种方法，其包括在管芯上制造管芯凸块，所述管芯凸块的形状和尺寸被设计成至少减小所使用的焊料材料的流动，以将管芯凸块附接到封装衬底 位于模具凸块下方的冶金（UBM）层。 有利地，该方法可以包括执行衬底回流操作以将封装衬底附接到管芯凸块，而不执行单独的晶片回流操作以回流管芯凸块。

公开(公告)号：US20090115057A1

公开(公告)日：2009-05-07

申请号：US12351689

申请日：2009-01-09

申请人： Sairam Agraharam ,  Carlton Hanna ,  Dongming He ,  Vasudeva Atluri ,  Debendra Mallik ,  Matthew Escobido ,  Sujit Sharan

发明人： Sairam Agraharam ,  Carlton Hanna ,  Dongming He ,  Vasudeva Atluri ,  Debendra Mallik ,  Matthew Escobido ,  Sujit Sharan

IPC分类号： H01L23/485

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13017 ,  H01L2224/13099 ,  H01L2224/16058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05099

摘要： In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.

摘要翻译： 在一个实施例中，本发明提供了一种方法，其包括在管芯上制造管芯凸块，所述管芯凸块的形状和尺寸被设计成至少减小所使用的焊料材料的流动，以将管芯凸块附接到封装衬底 位于模具凸块下方的冶金（UBM）层。 有利地，该方法可以包括执行衬底回流操作以将封装衬底附接到管芯凸块，而不执行单独的晶片回流操作以回流管芯凸块。

公开(公告)号：US20060214292A1

公开(公告)日：2006-09-28

申请号：US11087180

申请日：2005-03-22

申请人： Sairam Agraharam ,  Carlton Hanna ,  Dongming He ,  Vasudeva Atluri ,  Debendra Mallik ,  Matthew Escobido ,  Sujit Sharan

发明人： Sairam Agraharam ,  Carlton Hanna ,  Dongming He ,  Vasudeva Atluri ,  Debendra Mallik ,  Matthew Escobido ,  Sujit Sharan

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13017 ,  H01L2224/13099 ,  H01L2224/16058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05099

摘要： In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.

公开(公告)号：US09129958B2

公开(公告)日：2015-09-08

申请号：US13995917

申请日：2011-12-22

申请人： Debendra Mallik ,  Ram S. Viswanath ,  Sriram Srinivasan ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sairam Agraharam

发明人： Debendra Mallik ,  Ram S. Viswanath ,  Sriram Srinivasan ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sairam Agraharam

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L23/13 ,  H01L25/065

CPC分类号： H01L23/49838 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00

摘要： 3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.

摘要翻译： 描述了具有窗口插入件的3D集成电路封装和形成这种半导体封装的方法。 例如，半导体封装包括衬底。 顶部半导体管芯设置在衬底上方。 具有窗口的插入件设置在基板和顶部半导体管芯之间并与之互连。 底部半导体管芯设置在插入件的窗口中并且互连到顶部半导体管芯。 在另一示例中，半导体封装包括衬底。 顶部半导体管芯设置在衬底上方。 插入器设置在衬底和顶部半导体管芯之间并且互连到衬底和顶部半导体管芯。 底部半导体管芯设置在与插入器相同的平面中并且互连到顶部半导体管芯。

公开(公告)号：US09526285B2

公开(公告)日：2016-12-27

申请号：US13717909

申请日：2012-12-18

申请人： Aleksandar Aleksov ,  Ravindranath V. Mahajan ,  Sairam Agraharam ,  Ian A. Young ,  John C. Johnson ,  Debendra Mallik ,  John S. Guzek

发明人： Aleksandar Aleksov ,  Ravindranath V. Mahajan ,  Sairam Agraharam ,  Ian A. Young ,  John C. Johnson ,  Debendra Mallik ,  John S. Guzek

IPC分类号： H05K1/02 ,  H05K3/30 ,  A41D31/00 ,  H05K1/03 ,  H05K1/18 ,  H05K3/32 ,  H05K3/34

CPC分类号： A41D31/00 ,  H05K1/0274 ,  H05K1/038 ,  H05K1/188 ,  H05K3/323 ,  H05K3/3436 ,  Y10T29/4913

摘要： A flexible computing fabric and a method of forming thereof. The flexible computing fabric includes an electronic substrate including one or more channels and including at least two ends. At least one computational element is mounted on the electronic substrate between the two ends and at least one functional element is mounted on the electronic substrate between the two ends. The channels form an interconnect between the elements. In addition, the electronic substrate is flexible and exhibits a flexural modulus in the range of 0.1 GPa to 30 GPa.

摘要翻译： 一种灵活的计算结构及其形成方法。 柔性计算结构包括包括一个或多个通道并且包括至少两个端部的电子基板。 至少一个计算元件安装在两端之间的电子基板上，并且至少一个功能元件安装在两端之间的电子基板上。 通道形成元件之间的互连。 此外，电子基板是柔性的并且具有在0.1GPa至30GPa范围内的挠曲模量。

公开(公告)号：US20140191419A1

公开(公告)日：2014-07-10

申请号：US13995917

申请日：2011-12-22

申请人： Debendra Mallik ,  Ram S. Viswanath ,  Sriram Srinivasan ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sairam Agraharam

发明人： Debendra Mallik ,  Ram S. Viswanath ,  Sriram Srinivasan ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sairam Agraharam

IPC分类号： H01L25/065 ,  H01L23/498

CPC分类号： H01L23/49838 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00

摘要： 3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.

摘要翻译： 描述了具有窗口插入件的3D集成电路封装和形成这种半导体封装的方法。 例如，半导体封装包括衬底。 顶部半导体管芯设置在衬底上方。 具有窗口的插入件设置在基板和顶部半导体管芯之间并与之互连。 底部半导体管芯设置在插入件的窗口中并且互连到顶部半导体管芯。 在另一示例中，半导体封装包括衬底。 顶部半导体管芯设置在衬底上方。 插入器设置在衬底和顶部半导体管芯之间并且互连到衬底和顶部半导体管芯。 底部半导体管芯设置在与插入器相同的平面中并且互连到顶部半导体管芯。

公开(公告)号：US20150001732A1

公开(公告)日：2015-01-01

申请号：US13929001

申请日：2013-06-27

申请人： Debendra Mallik ,  Robert L. Sankman ,  Sujit Sharan

发明人： Debendra Mallik ,  Robert L. Sankman ,  Sujit Sharan

IPC分类号： H01L23/00

CPC分类号： H01L24/09 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/26 ,  H01L24/32 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0903 ,  H01L2224/09181 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/014

摘要： An apparatus includes at least a first integrated circuit (IC) and a wafer-fabricated space transformer (ST). The IC includes bonding pads of a first inter-pad pitch on a bottom surface. The ST includes a top surface having bonding pads of the first inter-pad pitch, and at least a portion of the bonding pads of the first IC are bonded to the bonding pads of the top surface. The ST includes a bottom surface having bonding pads of a second inter-pad pitch, at least one dielectric insulating layer between the top surface and the bottom surface, and conductive interconnect in the dielectric layer configured to provide electrical continuity between the bonding pads of the top surface and the bonding pads of the bottom surface.

摘要翻译： 装置至少包括第一集成电路（IC）和晶片制造的空间变换器（ST）。 该IC包括在底面上的第一间隔间距的接合焊盘。 ST包括具有第一衬垫间距的接合焊盘的顶表面，并且第一IC的至少一部分接合焊盘接合到顶表面的接合焊盘。 ST包括具有第二垫间间距的接合焊盘的底表面，在顶表面和底表面之间的至少一个介电绝缘层，以及介电层中的导电互连，其被配置为在 顶面和底面的接合垫。

公开(公告)号：US10242942B2

公开(公告)日：2019-03-26

申请号：US15127708

申请日：2014-04-25

申请人： Mathew J. Manusharow ,  Dustin P. Wood ,  Debendra Mallik

发明人： Mathew J. Manusharow ,  Dustin P. Wood ,  Debendra Mallik

IPC分类号： H01L23/48 ,  H01L23/50 ,  H01L23/00 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/525

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.

公开(公告)号：US09530758B2

公开(公告)日：2016-12-27

申请号：US14750811

申请日：2015-06-25

申请人： Debendra Mallik ,  Robert L. Sankman

发明人： Debendra Mallik ,  Robert L. Sankman

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/82 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/051 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81986 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/01079 ,  H01L2224/11

摘要： 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.