公开(公告)号：US20240047319A1

公开(公告)日：2024-02-08

申请号：US18125348

申请日：2023-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho PARK ,  Gyuho Kang ,  Sung Keun Park ,  Seong-Hoon Bae ,  Jaemok Jung ,  Ju-ll Choi

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L21/4853 ,  H01L21/563 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/48227 ,  H01L24/48

Abstract: A semiconductor package includes a first substrate, a semiconductor chip on the first substrate, a second substrate spaced apart from the first substrate, a wire spaced apart from a lateral surface of the semiconductor chip and connecting the first substrate to the second substrate, a mold structure on a top surface of the semiconductor chip, the lateral surface of the semiconductor chip, and a lateral surface of the wire, and an under-fill pattern on the lateral surface of the wire and is between the wire and the mold structure.

公开(公告)号：US20170062308A1

公开(公告)日：2017-03-02

申请号：US15151079

申请日：2016-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-ll Choi ,  Hyo-Ju Kim ,  Yeun-Sang Park ,  Atsushi Fujisaki ,  Kwang-Jin Moon ,  Byung-Lyul Park

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/481 ,  H01L21/486 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0501 ,  H01L2924/05032 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.

Abstract translation: 一种半导体器件包括穿透衬底的通孔结构，所述通孔结构的一部分在所述衬底的表面上暴露，所述保护层图案结构设置在所述衬底的表面上并且包括第一保护层图案和第二保护 所述第一保护层图案围绕所述通孔结构的所述暴露部分的下侧壁并暴露所述通孔结构的所述暴露部分的上侧壁，所述第二保护层图案暴露所述第一保护的顶表面的一部分 所述衬垫结构设置在所述通孔结构和所述保护层图案结构上并且覆盖由所述第二保护层图案暴露的所述第一保护层图案的顶表面。