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    Flip-chip semiconductor device with enhanced reliability and manufacturing efficiency, and the method for under filling the same
    2.
    发明授权
    Flip-chip semiconductor device with enhanced reliability and manufacturing efficiency, and the method for under filling the same 有权
    具有提高的可靠性和制造效率的倒装芯片半导体器件，以及用于填充其的方法

    公开(公告)号：US6153939A

    公开(公告)日：2000-11-28

    申请号：US317354

    申请日：1999-05-24

    申请人： Wei-Chung Wang ,  Hsueh-Te Wang ,  Jen-Kuang Fang ,  Su Tao

    发明人： Wei-Chung Wang ,  Hsueh-Te Wang ,  Jen-Kuang Fang ,  Su Tao

    IPC分类号： H01L21/56 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

    CPC分类号： H01L21/563 ,  H01L24/28 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/15151 ,  H01L2924/351

    摘要： A flip-chip semiconductor device and a method for under filling the flip-chip semiconductor device are disclosed. The flip-chip semiconductor device is provided with a substrate and a die having a plurality of solder bumps for connecting to the substrate. Encapsulation material is under filled between the die and the substrate. The substrate has a non-mask area defied in a center portion thereof while the remaining surface area is covered by a solder mask. The non-mask area defines a hole in the center thereof so that the encapsulation material can be dispensed along all sides of the die to flow toward the non-mask area and stop when reaching the non-mask area whereby the encapsulation material does not block the hole and air between said die and the substrate is limited in a void formed around the hole and communicated with the atmosphere via the hole.

    摘要翻译： 公开了一种倒装芯片半导体器件和用于填充倒装芯片半导体器件的方法。 倒装芯片半导体器件设置有具有用于连接到衬底的多个焊料凸块的衬底和管芯。 封装材料在模具和基板之间被填充。 基板在其中心部分具有不掩蔽的非掩模区域，而剩余表面积被焊接掩模覆盖。 非掩模区域在其中心限定一个孔，使得封装材料可以沿芯片的所有侧面分配以流向非掩模区域，并在达到非掩模区域时停止，从而封装材料不会阻塞 所述模具和基板之间的孔和空气被限制在形成在孔周围并且经由孔与大气连通的空隙中。

    Chip-scale semiconductor package
    10.
    发明授权
    Chip-scale semiconductor package 有权
    芯片级半导体封装

    公开(公告)号：US06150730A

    公开(公告)日：2000-11-21

    申请号：US349231

    申请日：1999-07-08

    申请人： Chih-Ming Chung ,  Kuo-Pin Yang ,  Jen-Kuang Fang ,  Su Tao

    发明人： Chih-Ming Chung ,  Kuo-Pin Yang ,  Jen-Kuang Fang ,  Su Tao

    IPC分类号： H01L23/495 ,  H01L23/498 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/4951 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/50 ,  H01L2924/14

    摘要： A chip-scale semiconductor package mainly includes a semiconductor chip, a substrate and a package body. Said chip is attached onto said substrate by an adhesive layer. Said chip has a plurality of bonding pads formed thereon. Said adhesive layer has an aperture corresponding to the bonding pads of said chip such that the bonding pads can be exposed within an aperture. Said substrate has several through-holes respectively corresponding to the bonding pads of said chip and parts of the area around the edge of said chip for dispensing of encapsulant after the soldering of leads of said substrate to the bonding pads of said chip. The encapsulant dispensed into the through-holes can flow from the surface of said chip to the edge thereof. Said package body has one portion provided within the through-hole of said substrate and another portion provided around the edge of said chip whereby encapsulation process is accomplished without having to turn the whole semiconductor package device.

    摘要翻译： 芯片级半导体封装主要包括半导体芯片，基板和封装体。 所述芯片通过粘合剂层附着在所述基板上。 所述芯片具有形成在其上的多个接合焊盘。 所述粘合剂层具有对应于所述芯片的焊盘的孔，使得焊盘可以暴露在孔内。 所述衬底具有分别对应于所述芯片的焊盘和所述芯片的边缘周围区域的部分的多个通孔，用于在将所述衬底的引线焊接到所述芯片的焊盘之后分配密封剂。 分配到通孔中的密封剂可以从所述芯片的表面流动到其边缘。 所述封装体具有设置在所述基板的通孔内的一部分和设置在所述芯片的边缘周围的另一部分，从而实现封装处理而不必转动整个半导体封装器件。