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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230137806A1

    公开(公告)日：2023-05-04

    申请号：US17669319

    申请日：2022-02-10

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Huai-Ying Huang ,  Yu-Ming Lin

    IPC分类号： H01L27/11 ,  H01L23/535

    摘要： A semiconductor device includes a semiconductor structure, a logic circuit, a plurality of first memory cells and through vias. The logic circuit is disposed at a first level over the semiconductor substrate. The first memory cells are disposed at a second level over the semiconductor substrate, wherein the second level is stacked on top and overlapped with the first level. Each of the first memory cells include a latch circuit and conductive elements. The latch circuit is formed of N-type field effect transistors (NFETs) and P-type field effect transistors (PFETs). The conductive elements are extending above the NFETs and the PFETs and electrically coupled to the NFETs and the PFETs. The through vias are extending from the second level to the first level and electrically connecting the conductive elements to the logic circuit by a vertical conduction path.

    Stable SRAM Cell
    3.
    发明申请
    Stable SRAM Cell 有权
    稳定的SRAM单元

    公开(公告)号：US20140254249A1

    公开(公告)日：2014-09-11

    申请号：US14285362

    申请日：2014-05-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Huai-Ying Huang ,  Yu-Kuan Lin ,  Sheng Chiang Hung ,  Feng-Ming Chang ,  Jui-Lin Chen ,  Ping-Wei Wang

    IPC分类号： G11C11/412 ,  G11C11/419

    CPC分类号： G11C11/412 ,  G11C11/419

    摘要： SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

    摘要翻译： 描述SRAM单元和SRAM单元阵列。 在一个实施例中，SRAM单元包括与第一反相器交叉耦合的第一反相器和第二反相器，以形成第一数据存储节点和用于锁存值的互补的第二数据存储节点。 SRAM单元还包括第一栅极晶体管和开关晶体管。 第一栅极晶体管的第一源极/漏极耦合到第一数据存储节点，并且第一栅极晶体管的第二源极/漏极耦合到第一位线。 开关晶体管的第一源极/漏极耦合到第一通过栅极晶体管的栅极。

    Stable SRAM Cell
    4.
    发明申请
    Stable SRAM Cell 有权
    稳定的SRAM单元

    公开(公告)号：US20130250660A1

    公开(公告)日：2013-09-26

    申请号：US13864873

    申请日：2013-04-17

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Huai-Ying Huang ,  Yu-Kuan Lin ,  Sheng Chiang Hung ,  Feng-Ming Chang ,  Jui-Lin Chen ,  Ping-Wei Wang

    IPC分类号： G11C11/412

    CPC分类号： G11C11/412 ,  G11C11/419

    摘要： SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

    摘要翻译： 描述SRAM单元和SRAM单元阵列。 在一个实施例中，SRAM单元包括与第一反相器交叉耦合的第一反相器和第二反相器，以形成第一数据存储节点和用于锁存值的互补的第二数据存储节点。 SRAM单元还包括第一栅极晶体管和开关晶体管。 第一栅极晶体管的第一源极/漏极耦合到第一数据存储节点，并且第一栅极晶体管的第二源极/漏极耦合到第一位线。 开关晶体管的第一源极/漏极耦合到第一通过栅极晶体管的栅极。

    Method for programming memory
    6.
    发明授权
    Method for programming memory 有权

    公开(公告)号：US12040018B2

    公开(公告)日：2024-07-16

    申请号：US18077580

    申请日：2022-12-08

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： I-Che Lee ,  Huai-Ying Huang

    IPC分类号： G11C16/10 ,  G11C13/00

    CPC分类号： G11C13/0069 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004

    摘要： A method includes setting a current level of a write signal to a first non-zero value for a first period of time. The write signal is provided to a memory element during the first period of time. The current level of the write signal is adjusted from the first non-zero value to a second non-zero value, different from the first non-zero value, for a second period of time. The write signal is provided to the memory element during the second period of time. The current level of the write signal is adjusted from the second non-zero value to a third value, different from the first non-zero value and different from the second non-zero value, for a third period of time. The write signal is provided to the memory element during the third period of time.