公开(公告)号：US20220102580A1

公开(公告)日：2022-03-31

申请号：US17422867

申请日：2020-01-16

Applicant: The Regents of the University of California

Inventor： Caroline E. Reilly ,  Umesh K. Mishra ,  Stacia Keller ,  Steven P. DenBaars

IPC: H01L33/00 ,  H01L31/18 ,  H01L33/02

Abstract: A method for fabricating a device, as well as the device itself, which includes growing a bonding layer on a first wafer or substrate, wherein the bonding layer includes at least partially relaxed features; and then bonding a second wafer or substrate to the features in on the first wafer or substrate, to cap and contact the features with separately grown material.

公开(公告)号：US20210399121A1

公开(公告)日：2021-12-23

申请号：US17353665

申请日：2021-06-21

Applicant: The Regents of the University of California

Inventor： Brian Romanczyk ,  Umesh K. Mishra ,  Pawana Shrestha ,  Matthew Guidry ,  James Buckwalter ,  Stacia Keller ,  Rohit Reddy Karnaty

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/267

Abstract: Derivative cancellation techniques have been used to linearize transistors using multiple discreet devices. However at frequencies approaching and in the mm-wave regime the use of individual devices no longer works due to the parasitics associated with combining the devices. In this invention device structures are described which apply the derivative cancellation technique in a single device thus removing the detrimental impact of combining. In one example, an N-polar transistor structure includes a channel; a cap structure comprising a plurality of cap layers on or above the channel; a source contact and a drain contact to the channel; and a castellated, stepped, or varying pattern formed in the cap layers so that gate metal deposited on the pattern forms at least two different threshold voltages and current combines in the ohmic region with essentially zero parasitic inductance.

公开(公告)号：US20210399096A1

公开(公告)日：2021-12-23

申请号：US17291842

申请日：2019-11-07

Applicant: The Regents of the University of California

Inventor： Umesh K. Mishra ,  Stacia Keller ,  Elaheh Ahmadi ,  Chirag Gupta ,  Yusuke Tsukada

IPC: H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/737 ,  H01L27/092 ,  H01L29/78 ,  H01L33/32

Abstract: Strain is used to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition.

公开(公告)号：US11101379B2

公开(公告)日：2021-08-24

申请号：US16461505

申请日：2017-11-16

Applicant: The Regents of the University of California

Inventor： Brian Romanczyk ,  Haoran Li ,  Elaheh Ahmadi ,  Steven Wienecke ,  Matthew Guidry ,  Xun Zheng ,  Stacia Keller ,  Umesh K. Mishra

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205

Abstract: A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As illustrated herein, a thin InGaN layer introduced in the channel increases the carrier density, reduces the electric field in the channel, and increases the carrier mobility. The dependence of p on InGaN thickness (tInGaN) and indium composition (xIn) was investigated for different channel thicknesses. With optimized tInGaN and xIn, significant improvements in electron mobility were observed. For a 6 nm channel HEMT, the electron mobility increased from 606 to 1141 cm2/(V·s) when the 6 nm thick pure GaN channel was replaced by the 4 nm GaN/2 nm In0.1Ga0.9N composite channel.

公开(公告)号：US20170125574A1

公开(公告)日：2017-05-04

申请号：US15344377

申请日：2016-11-04

Applicant: The Regents of the University of California

Inventor： Srabanti Chowdhury ,  Jeonghee Kim ,  Chirag Gupta ,  Stacia Keller ,  Silvia H. Chan ,  Umesh K. Mishra

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/205 ,  H01L29/20 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/0623 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/861

Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

公开(公告)号：US20160163846A1

公开(公告)日：2016-06-09

申请号：US15009509

申请日：2016-01-28

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Xiang Liu ,  Umesh K. Mishra ,  Stacia Keller ,  Jeonghee Kim ,  Matthew Laurent ,  Jing Lu ,  Ramya Yeluri ,  Silvia H. Chan

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7787 ,  C30B25/02 ,  C30B29/20 ,  C30B29/406 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.

公开(公告)号：US20150200286A1

公开(公告)日：2015-07-16

申请号：US14597989

申请日：2015-01-15

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Xiang Liu ,  Umesh K. Mishra ,  Stacia Keller ,  Jeonghee Kim ,  Matthew Laurent ,  Jing Lu ,  Ramya Yeluri ,  Silvia H. Chan

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7787 ,  C30B25/02 ,  C30B29/20 ,  C30B29/406 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.

Abstract translation: 一种制造III族氮化物半导体器件的方法，包括在氧化物生长和III族氮化物半导体的生长之间不暴露于空气中，依次生长III族氮化物半导体和氧化物以形成氧化物/ III族氮化物界面 。

公开(公告)号：US12211955B2

公开(公告)日：2025-01-28

申请号：US17576716

申请日：2022-01-14

Applicant: The Regents of the University of California

Inventor： Kamruzzaman Khan ,  Elaheh Ahmadi ,  Stacia Keller ,  Christian Wurm ,  Umesh K. Mishra

IPC: H01L33/32 ,  H01L33/00

Abstract: A substrate comprising a III-N base layer comprising a first portion and a second portion, the first portion of the III-N base layer having a first natural lattice constant and a first dislocation density; and a first III-N layer having a second natural lattice constant and a second dislocation density on the III-N base layer, the first III-N layer having a thickness greater than 10 nm. An indium fractional composition of the first III-N layer is greater than 0.1; the second natural lattice constant is at least 1% greater than the first natural lattice constant; a strain-induced lattice constant of the first III-N layer is greater than 1.0055 times the first natural lattice constant; and the second dislocation density is less than 1.5 times the first dislocation density.

公开(公告)号：US12159929B1

公开(公告)日：2024-12-03

申请号：US17114307

申请日：2020-12-07

Applicant: The Regents of the University of California

Inventor： Stacia Keller ,  Umesh K. Mishra

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/15 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: An electronic device including a substrate a group III-V layer on or above the substrate, wherein the III-V layer has an in-plane lattice constant that is greater than that of gallium nitride or wherein the III-V layer is at least partially relaxed; and an active region including a coherently strained group III-V channel layer on or above the III-V layer; wherein electron mobility in the channel layer is increased by the strain. Structures with an in-plane lattice constant that is smaller than that of gallium nitride are used for increasing the hole mobility by strain.

公开(公告)号：US20240063340A1

公开(公告)日：2024-02-22

申请号：US17642057

申请日：2020-09-10

Applicant: The Regents of the University of California

Inventor： Stacia Keller ,  Umesh K. Mishra ,  Shubhra Pasayat ,  Chirag Gupta

IPC: H01L33/32 ,  H01L33/16 ,  H01L33/12 ,  H01L25/075 ,  H01L33/20

CPC classification number: H01L33/32 ,  H01L33/16 ,  H01L33/12 ,  H01L25/0753 ,  H01L33/20

Abstract: The present disclosure describes porous GaN layers and/or compliant substrates used to enable relaxation of previously strained top layers and the deposition of relaxed or partially relaxed on top. Relaxed In GaN layers are fabricated without generation of crystal defects, which can serve as base layers for high performance long wavelength light emitting devices (LEDs, lasers) solar cells, or strain engineered transistors. Similarly, relaxed AlGaN layers can serve as base layers for high performance short wavelength UV light emitting devices (LEDs, lasers) solar cells, or wide bandgap transistors.