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    READING OF START-UP INFORMATION FROM DIFFERENT MEMORY REGIONS OF A MEMORY SYSTEM
    3.
    发明申请
    READING OF START-UP INFORMATION FROM DIFFERENT MEMORY REGIONS OF A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20190332285A1

    公开(公告)日：2019-10-31

    申请号：US16506475

    申请日：2019-07-09

    申请人： Toshiba Memory Corporation

    发明人： Riki SUZUKI ,  Toshikatsu HIDA ,  Takehiko AMAKI ,  Shunichi IGAHARA

    IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/0875 ,  G06F11/10 ,  G11C29/00 ,  G11C29/52

    摘要： A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.

    MEMORY SYSTEM CAPABLE OF ACCESSING MEMORY CELL ARRAYS IN PARALLEL
    9.
    发明申请
    MEMORY SYSTEM CAPABLE OF ACCESSING MEMORY CELL ARRAYS IN PARALLEL 审中-公开

    公开(公告)号：US20190095108A1

    公开(公告)日：2019-03-28

    申请号：US16199803

    申请日：2018-11-26

    申请人： Toshiba Memory Corporation

    发明人： Sayano AGA ,  Toshikatsu HIDA ,  Riki SUZUKI

    IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/10

    CPC分类号： G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0897 ,  G06F12/10 ,  G06F2212/1024 ,  G06F2212/2022 ,  G06F2212/7201

    摘要： According to one embodiment, a memory system includes a first memory as a nonvolatile memory storing first data, second data as a translation table for accessing the first data, third data, fourth data as a translation table for accessing the third data, and including two memory cell arrays which are accessible in parallel, a second memory in which the second and fourth data is storable, and which stores a management table for managing information about whether the second and fourth data is stored in the second memory, a controller checking whether the second and fourth data is stored in the second memory based on the management table, a third memory storing an order of executing commands to be issued to the first memory, and a scheduler scheduling the order based on a result of the checking, two of a first command for reading the first data, a second command for reading the second data, a third command for reading the third data and a fourth command for reading the fourth data being executed in parallel in the order.