公开(公告)号：US20160276314A1

公开(公告)日：2016-09-22

申请号：US15166674

申请日：2016-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Ming Ching ,  Ching-Wen Hsiao ,  Tsung-Ding Wang ,  Ming Hung Tseng ,  Chen-Shien Chen

IPC: H01L25/065 ,  H01L23/473 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/46 ,  H01L23/473 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An integrated circuit structure includes a die including a semiconductor substrate, dielectric layers over the semiconductor substrate, an interconnect structure including metal lines and vias in the dielectric layers, a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers, and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

Abstract translation: 集成电路结构包括具有半导体衬底的模具，半导体衬底上的电介质层，介电层中包括金属线和通路的互连结构，从半导体衬底内部延伸到电介质层内部的多个沟道，以及 电介质膜在多个通道的互连结构和密封部分上。 多个通道被配置成允许流体流过。

公开(公告)号：US20150214166A1

公开(公告)日：2015-07-30

申请号：US14685136

申请日：2015-04-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Ming Ching

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02126 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/16059 ,  H01L2224/16147 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01002 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit.

Abstract translation: 堆叠和对准多个集成电路的方法和系统。 该方法包括以下步骤：提供具有至少一个漏斗形插座的第一集成电路，提供第二集成电路，将第二集成电路上的至少一个突起与至少一个漏斗形插座对准，并将第一集成电路 集成电路到第二集成电路。 该系统包括具有至少一个漏斗形插座，设置在漏斗形插座内部的金属化扩散屏障和第二集成电路的第一集成电路。 所述至少一个漏斗形插座适于接收第二集成电路的一部分。

公开(公告)号：US20240312930A1

公开(公告)日：2024-09-19

申请号：US18673328

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Ming Ching ,  Shu-Shen Yeh ,  Chien-Hung Chen ,  Hui-Chang Yu ,  Yu-Min Cheng

IPC: H01L23/552 ,  H01L21/50 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/552 ,  H01L21/50 ,  H01L23/16 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/08 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/165 ,  H01L2224/08113 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/32245 ,  H01L2924/16195

Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

公开(公告)号：US20220148979A1

公开(公告)日：2022-05-12

申请号：US17203732

申请日：2021-03-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Ming Ching ,  Shu-Shen Yeh ,  Chien-Hung Chen ,  Hui-Chang Yu ,  Yu-Min Cheng

IPC: H01L23/552 ,  H01L23/16 ,  H01L23/31 ,  H01L21/50

Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

公开(公告)号：US09355933B2

公开(公告)日：2016-05-31

申请号：US14132515

申请日：2013-12-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Ming Ching ,  Ching-Wen Hsiao ,  Tsung-Ding Wang ,  Ming Hung Tseng ,  Chen-Shien Chen

IPC: H01L23/46 ,  H01L23/473 ,  H01L23/48 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/46 ,  H01L23/473 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

Abstract translation: 集成电路结构包括：具有半导体衬底的裸片; 半导体衬底上的电介质层; 包括电介质层中的金属线和通孔的互连结构; 从所述半导体衬底的内部延伸到所述电介质层的内部的多个沟道; 以及在所述多个通道的互连结构和密封部分上的电介质膜。 多个通道被配置成允许流体流过。

公开(公告)号：US20140103540A1

公开(公告)日：2014-04-17

申请号：US14132515

申请日：2013-12-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Ming Ching ,  Ching-Wen Hsiao ,  Tsung-Ding Wang ,  Ming Hung Tseng ,  Chen-Shien Chen

IPC: H01L23/46 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/46 ,  H01L23/473 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

Abstract translation: 集成电路结构包括：具有半导体衬底的裸片; 半导体衬底上的电介质层; 包括电介质层中的金属线和通孔的互连结构; 从所述半导体衬底的内部延伸到所述电介质层的内部的多个沟道; 以及在所述多个通道的互连结构和密封部分上的电介质膜。 多个通道被配置成允许流体流过。

公开(公告)号：US20230230935A1

公开(公告)日：2023-07-20

申请号：US18187662

申请日：2023-03-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Ming Ching ,  Shu-Shen Yeh ,  Chien-Hung Chen ,  Hui-Chang Yu ,  Yu-Min Cheng

IPC: H01L25/16 ,  H01L25/065 ,  H01L23/31 ,  H01L23/16 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L25/165 ,  H01L25/0652 ,  H01L23/3107 ,  H01L23/16 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/552 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L2224/08113 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/32245 ,  H01L2924/16195

Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

公开(公告)号：US09859252B2

公开(公告)日：2018-01-02

申请号：US15166674

申请日：2016-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Ming Ching ,  Ching-Wen Hsiao ,  Tsung-Ding Wang ,  Ming Hung Tseng ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/522 ,  H01L25/065 ,  H01L23/473 ,  H01L23/48 ,  H01L23/46 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/46 ,  H01L23/473 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An integrated circuit structure includes a die including a semiconductor substrate, dielectric layers over the semiconductor substrate, an interconnect structure including metal lines and vias in the dielectric layers, a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers, and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

公开(公告)号：US09673174B2

公开(公告)日：2017-06-06

申请号：US14596088

申请日：2015-01-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Ding Wang ,  Chen-Shien Chen ,  Kai-Ming Ching ,  Bo-I Lee ,  Chien-Hsun Lee

IPC: H01L29/40 ,  H01L25/065 ,  H01L21/18 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/187 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16113 ,  H01L2224/16146 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/00014

Abstract: System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.

公开(公告)号：US12021042B2

公开(公告)日：2024-06-25

申请号：US18187662

申请日：2023-03-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Ming Ching ,  Shu-Shen Yeh ,  Chien-Hung Chen ,  Hui-Chang Yu ,  Yu-Min Cheng

IPC: H01L25/16 ,  H01L21/50 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L21/50 ,  H01L23/16 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/08 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/165 ,  H01L2224/08113 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/32245 ,  H01L2924/16195

Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.