公开(公告)号：US07614142B2

公开(公告)日：2009-11-10

申请号：US12068272

申请日：2008-02-05

申请人： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

发明人： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

IPC分类号： H05K3/36 ,  H01L23/29

CPC分类号： H01L23/50 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/0044 ,  H05K3/20 ,  H05K3/4614 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0733 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599

摘要： A method for fabricating an interposer includes: forming on one primary surface of a first substrate a thin-film capacitor including a first capacitor electrode, a crystalline capacitor dielectric film formed on the first electrode and a second capacitor electrode formed on the dielectric film; and forming on the primary surface of the first substrate and the capacitor a first layer as semi-cured, and a first partial electrode to be a part of a through-electrode, buried in the first resin layer and electrically connected to the first electrode or the second electrode. The method further includes cutting an upper part of the first partial electrode and an upper part of the first resin layer with a cutting tool; forming on one primary surface of a second substrate a second resin layer as semi-cured, and a second partial electrode to be a part of the through-electrode, buried in the second resin layer and disposed in alignment with the first partial electrode; cutting an upper part of the second partial electrode and an upper part of the second resin layer with a cutting tool; making thermal processing with the first resin layer and the second resin layer in close contact with each other to adhere the first resin and the second resin layer to each other while jointing the first and second partial electrodes to each other; removing the first substrate; forming on said one primary surface of the second substrate a third resin layer, covering the thin-film capacitor, burying a third partial electrode to be a part of the through-electrode in the third resin layer, supporting the third resin layer by a supporting substrate; and removing the second substrate.

摘要翻译： 一种用于制造插入件的方法，包括：在第一基板的一个主表面上形成薄膜电容器，薄膜电容器包括第一电容器电极，形成在第一电极上的晶体电容器电介质膜和形成在电介质膜上的第二电容器电极; 并且在第一基板和电容器的主表面上形成半固化的第一层，以及作为通孔的一部分的第一部分电极，埋入第一树脂层中并电连接到第一电极或 第二电极。 该方法还包括用切割工具切割第一部分电极的上部和第一树脂层的上部; 在第二基板的一个主表面上形成半固化的第二树脂层和作为所述通孔的一部分的第二部分电极，所述第二部分电极埋入所述第二树脂层中并与所述第一部分电极对准; 用切割工具切割第二部分电极的上部和第二树脂层的上部; 使第一树脂层和第二树脂层彼此紧密接触进行热处理，以将第一和第二部分电极彼此接合，使第一树脂和第二树脂层彼此粘合; 去除第一衬底; 在所述第二基板的所述一个主表面上形成覆盖所述薄膜电容器的第三树脂层，在所述第三树脂层中埋设作为所述贯通电极的一部分的第三部分电极，通过支撑所述第三树脂层 基质; 并移除第二基板。

公开(公告)号：US20080134499A1

公开(公告)日：2008-06-12

申请号：US12068272

申请日：2008-02-05

申请人： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

发明人： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

IPC分类号： H05K3/46

CPC分类号： H01L23/50 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/0044 ,  H05K3/20 ,  H05K3/4614 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0733 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599

摘要： The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.

摘要翻译： 插入件包括由多个树脂层68,20,32,48形成的基座8; 掩埋在所述多个树脂层的第一树脂层68和所述多个树脂层的第二树脂层20之间的薄膜电容器18a，18b，其包括第一电容器电极12a，12b，第二电容器电极16 与第一电容器电极12a，12b和第二电容器电极16相对，以及形成在第一电容器电极12a，12b和第二电容器电极16之间的相对介电常数为200或更大的电容器电介质膜14 ; 通过基座8形成并电连接到第一电容器电极12a，12b的第一贯通电极77a; 以及通过基底8形成并电连接到第二电容器电极16的第二贯通电极77b。

公开(公告)号：US07355290B2

公开(公告)日：2008-04-08

申请号：US11338857

申请日：2006-01-25

申请人： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

发明人： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

IPC分类号： H01L23/29

CPC分类号： H01L23/50 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/0044 ,  H05K3/20 ,  H05K3/4614 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0733 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599

摘要： The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.

摘要翻译： 插入件包括由多个树脂层68,20,32,48形成的基座8; 掩埋在所述多个树脂层的第一树脂层68和所述多个树脂层的第二树脂层20之间的薄膜电容器18a，18b，其包括第一电容器电极12a，12b，第二电容器电极16 与第一电容器电极12a，12b和第二电容器电极16相对，以及形成在第一电容器电极12a，12b和第二电容器电极16之间的相对介电常数为200或更大的电容器电介质膜14 ; 通过基座8形成并电连接到第一电容器电极12a，12b的第一贯通电极77a; 以及通过基底8形成并电连接到第二电容器电极16的第二贯通电极77b。

公开(公告)号：US20070090546A1

公开(公告)日：2007-04-26

申请号：US11338857

申请日：2006-01-25

申请人： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John Baniecki ,  Kazuaki Kurihara

发明人： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John Baniecki ,  Kazuaki Kurihara

IPC分类号： H01L23/29

CPC分类号： H01L23/50 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/0044 ,  H05K3/20 ,  H05K3/4614 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0733 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599

摘要： The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.

摘要翻译： 插入件包括由多个树脂层68,20,32,48形成的基座8; 掩埋在所述多个树脂层的第一树脂层68和所述多个树脂层的第二树脂层20之间的薄膜电容器18a，18b，其包括第一电容器电极12a，12b，第二电容器电极16 与第一电容器电极12a，12b和第二电容器电极16相对，以及形成在第一电容器电极12a，12b和第二电容器电极16之间的相对介电常数为200或更大的电容器电介质膜14 ; 通过基座8形成并电连接到第一电容器电极12a，12b的第一贯通电极77a; 以及通过基底8形成并电连接到第二电容器电极16的第二贯通电极77b。

公开(公告)号：US20080073110A1

公开(公告)日：2008-03-27

申请号：US11902251

申请日：2007-09-20

申请人： Takeshi Shioga ,  Kazuaki Kurihara ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi

发明人： Takeshi Shioga ,  Kazuaki Kurihara ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi

IPC分类号： H05K1/16 ,  H05K3/30

CPC分类号： H05K1/162 ,  H01L21/486 ,  H01L23/15 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/4605 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10378 ,  Y10T29/49002 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： The interposer includes a glass substrate 46 with first through-electrodes 47 buried in; a plurality of resin layers 68, 20, 32 supported by the glass substrate; thin film capacitors 18a, 18b buried between a first resin layer 68 of the plural resin layers and a second resin layer 20 of the plural resin layers and including the first capacitor electrodes 12a, 12b, the second capacitor electrodes 16 opposed to the first capacitor electrodes 12a, 12b, and a dielectric thin film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and the second through-electrodes 77a, 77b penetrating the plural resin layers 68, 20, 32, electrically connected to the first through-electrode 47 and electrically connected to the first capacitor electrode 12a, 12b or the second capacitor electrode 16.

摘要翻译： 插入件包括：第一贯通电极47被埋入的玻璃基板46; 由玻璃基板支撑的多个树脂层68,20,32; 埋在多个树脂层的第一树脂层68和多个树脂层的第二树脂层20之间并且包括第一电容器电极12a，12b的第二电容器电极16的薄膜电容器18a，18b， 形成在第一电容器电极12 a，12 b和第二电容器电极16之间的相对介电常数为200或更大的第一电容器电极12a，12b和电介质薄膜14，以及第二贯通电极77 a，77b穿透电连接到第一通孔47并与第一电容器电极12a，2b或第二电容器电极16电连接的多个树脂层68,20,32。

公开(公告)号：US08479386B2

公开(公告)日：2013-07-09

申请号：US12944904

申请日：2010-11-12

申请人： Takeshi Shioga ,  Kazuaki Kurihara ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi

发明人： Takeshi Shioga ,  Kazuaki Kurihara ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi

IPC分类号： H05K3/02

CPC分类号： H05K1/162 ,  H01L21/486 ,  H01L23/15 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/4605 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10378 ,  Y10T29/49002 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method for manufacturing an interposer including forming a capacitor over a semiconductor substrate; forming a first resin layer with a first partial electrode buried in over the semiconductor substrate and the capacitor; cutting an upper part of the first partial electrode and the first resin layer with a cutting tool; forming a second resin layer with a second partial electrode buried in over a glass substrate with a through-electrode buried in; cutting an upper part of the second partial electrode and the second resin layer with the cutting tool; making thermal processing with the first resin layer and the second resin layer adhered to each other while connecting the first partial electrode and the second partial electrode to each other; removing the semiconductor substrate; forming a third resin layer over the glass substrate, covering the capacitor; and burying a third partial electrode in the third resin layer.

摘要翻译： 一种用于制造包括在半导体衬底上形成电容器的插入器的方法; 形成第一树脂层，其中第一部分电极埋在半导体衬底和电容器之上; 用切割工具切割第一部分电极和第一树脂层的上部; 形成具有埋在玻璃基板上的第二部分电极的第二树脂层，其中埋入有通孔; 用切割工具切割第二部分电极和第二树脂层的上部; 在使第一部分电极和第二部分电极彼此连接的同时，使第一树脂层和第二树脂层彼此粘合; 去除半导体衬底; 在玻璃基板上形成第三树脂层，覆盖电容器; 并在第三树脂层中埋设第三部分电极。

公开(公告)号：US20110056068A1

公开(公告)日：2011-03-10

申请号：US12944904

申请日：2010-11-12

申请人： Takeshi Shioga ,  Kazuaki Kurihara ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi

发明人： Takeshi Shioga ,  Kazuaki Kurihara ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi

IPC分类号： H05K13/00

CPC分类号： H05K1/162 ,  H01L21/486 ,  H01L23/15 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/4605 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10378 ,  Y10T29/49002 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： The interposer includes a glass substrate 46 with first through-electrodes 47 buried in; a plurality of resin layers 68, 20, 32 supported by the glass substrate; thin film capacitors 18a, 18b buried between a first resin layer 68 of the plural resin layers and a second resin layer 20 of the plural resin layers and including the first capacitor electrodes 12a, 12b, the second capacitor electrodes 16 opposed to the first capacitor electrodes 12a, 12b, and a dielectric thin film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and the second through-electrodes 77a, 77b penetrating the plural resin layers 68, 20, 32, electrically connected to the first through-electrode 47 and electrically connected to the first capacitor electrode 12a, 12b or the second capacitor electrode 16.

公开(公告)号：US07863524B2

公开(公告)日：2011-01-04

申请号：US11902251

申请日：2007-09-20

申请人： Takeshi Shioga ,  Kazuaki Kurihara ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi

发明人： Takeshi Shioga ,  Kazuaki Kurihara ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi

IPC分类号： H05K1/16

CPC分类号： H05K1/162 ,  H01L21/486 ,  H01L23/15 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/4605 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10378 ,  Y10T29/49002 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： The interposer includes a glass substrate 46 with first through-electrodes 47 buried in; a plurality of resin layers 68, 20, 32 supported by the glass substrate; thin film capacitors 18a, 18b buried between a first resin layer 68 of the plural resin layers and a second resin layer 20 of the plural resin layers and including the first capacitor electrodes 12a, 12b, the second capacitor electrodes 16 opposed to the first capacitor electrodes 12a, 12b, and a dielectric thin film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and the second through-electrodes 77a, 77b penetrating the plural resin layers 68, 20, 32, electrically connected to the first through-electrode 47 and electrically connected to the first capacitor electrode 12a, 12b or the second capacitor electrode 16.

摘要翻译： 插入件包括：第一贯通电极47被埋入的玻璃基板46; 由玻璃基板支撑的多个树脂层68,20,32; 埋在多个树脂层的第一树脂层68和多个树脂层的第二树脂层20之间并且包括第一电容器电极12a，12b的薄膜电容器18a，18b，与第一电容器电极相对的第二电容器电极16 12a，12b和形成在第一电容器电极12a，12b和第二电容器电极16之间的相对介电常数为200以上的电介质薄膜14，以及贯穿多个树脂层68的第二贯通电极77a，77b ，20,32，与第一贯通电极47电连接，与第一电容电极12a，12b或第二电容电极16电连接。

公开(公告)号：US08962470B2

公开(公告)日：2015-02-24

申请号：US12413898

申请日：2009-03-30

申请人： Masataka Mizukoshi ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Keishiro Okamoto ,  Kazuo Teshirogi ,  Taiji Sakai

发明人： Masataka Mizukoshi ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Keishiro Okamoto ,  Kazuo Teshirogi ,  Taiji Sakai

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L24/81 ,  H01L21/4853 ,  H01L21/78 ,  H01L22/12 ,  H01L22/14 ,  H01L22/26 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/11464 ,  H01L2224/11602 ,  H01L2224/11632 ,  H01L2224/1184 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/29111 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73104 ,  H01L2224/749 ,  H01L2224/75 ,  H01L2224/75252 ,  H01L2224/81075 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2224/29099

摘要： A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.

摘要翻译： 半导体基板通过抽吸固定到基板支撑台的支撑面的后表面。 在这种情况下，半导体基板的厚度通过在后表面上的平坦化而被固定，并且后表面被强制地进入到通过吸力而不起伏的状态到支撑面，使得背面成为参考面 用于正面的平坦化。 在这种状态下，使用工具切割前表面上的Au突起和抗蚀剂掩模的表面层，从而使Au突起和抗蚀剂掩模平坦化，使得它们的表面变得连续平坦。 这可以以低成本和高速代替CMP来平坦化形成在基板上的微细凸块的表面。

公开(公告)号：US20050161814A1

公开(公告)日：2005-07-28

申请号：US11083926

申请日：2005-03-21

申请人： Masataka Mizukoshi ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Keishiro Okamoto ,  Kazuo Teshirogi ,  Taiji Sakai

发明人： Masataka Mizukoshi ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Keishiro Okamoto ,  Kazuo Teshirogi ,  Taiji Sakai

IPC分类号： H01L21/48 ,  H01L21/60 ,  H01L23/48 ,  H01L23/485

CPC分类号： H01L24/81 ,  H01L21/4853 ,  H01L21/78 ,  H01L22/12 ,  H01L22/14 ,  H01L22/26 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/11464 ,  H01L2224/11602 ,  H01L2224/11632 ,  H01L2224/1184 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/29111 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73104 ,  H01L2224/749 ,  H01L2224/75 ,  H01L2224/75252 ,  H01L2224/81075 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2224/29099

摘要： A semiconductor substrate (1) is secured by suction to a rear face (1b) of a supporting face (11a) of a substrate supporting table (11). In this event, the thickness of the semiconductor substrate (1) is made fixed by planarization on the rear face (1b), and the rear face (1b) is forcibly brought into a state free from undulation by the suction to the supporting face (11a), so that the rear face (1b) becomes a reference face for planarization of a front face (1a). In this state, a tool (10) is used to cut surface layers of Au projections (2) and a resist mask (12) on the front face (1a), thereby planarizing the Au projections (2) and the resist mask (12) so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.

摘要翻译： 半导体衬底（1）通过抽吸固定到衬底支撑台（11）的支撑面（11a）的后表面（1b）上。 在这种情况下，半导体衬底（1）的厚度通过在后表面（1b）上的平坦化而被固定，并且后表面（1b）被强制地进入到通过抽吸而不起伏的状态到支撑 面部（11a），使得背面（1b）成为用于使正面（1a）平坦化的基准面。 在该状态下，使用工具（10）来切割前表面（1a）上的Au突起（2）和抗蚀剂掩模（12）的表面层，从而使Au突起（2）和抗蚀剂掩模 12），使其表面变得连续平坦。 这可以以低成本和高速代替CMP来平坦化形成在基板上的微细凸块的表面。