公开(公告)号：US07868431B2

公开(公告)日：2011-01-11

申请号：US12391251

申请日：2009-02-23

申请人： Tao Feng ,  Xiaotian Zhang ,  François Hébert ,  Ming Sun

发明人： Tao Feng ,  Xiaotian Zhang ,  François Hébert ,  Ming Sun

IPC分类号： H01L23/495 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01F5/00

CPC分类号： H01L23/49861 ,  H01F17/0033 ,  H01F2027/2814 ,  H01L21/4832 ,  H01L21/563 ,  H01L23/495 ,  H01L23/4951 ,  H01L23/49548 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A power semiconductor package is disclosed with high inductance rating while exhibiting a reduced foot print. It has a bonded stack of power IC die at bottom, a power inductor at top and a circuit substrate, made of leadframe or printed circuit board, in the middle. The power inductor has a inductor core of closed magnetic loop. The circuit substrate has a first number of bottom half-coil forming conductive elements beneath the inductor core. A second number of top half-coil forming conductive elements, made of bond wires, three dimensionally formed interconnection plates or upper leadframe leads, are located atop the inductor core with both ends of each element connected to respective bottom half-coil forming conductive elements to jointly form an inductive coil enclosing the inductor core. A top encapsulant protectively encases the inductor core, the top half-coil forming conductive elements, the bottom half-coil forming conductive elements and the circuit substrate.

摘要翻译： 公开了一种功率半导体封装，其具有高电感额定值，同时显示出减少的脚印。 底部有一个电源IC芯片，顶部有一个功率电感器和一个由引线框或印刷电路板制成的电路基板。 功率电感器具有闭合磁环的电感芯。 电路衬底具有在电感器芯下方形成导电元件的第一数量的底部半线圈。 由接合线，三维形成的互连板或上引线框引线构成的第二数量的上半线圈形成导电元件位于电感器芯的顶部，每个元件的两端连接到形成导电元件的相应底部半线圈， 共同形成围绕电感器芯的感应线圈。 顶部密封剂保护性地封装电感器芯，顶部半线圈形成导电元件，底部半线圈形成导电元件和电路衬底。

公开(公告)号：US20090160045A1

公开(公告)日：2009-06-25

申请号：US11963690

申请日：2007-12-21

申请人： Ming Sun ,  Tao Feng ,  Francois Hebert ,  Yueh-Se Ho

发明人： Ming Sun ,  Tao Feng ,  Francois Hebert ,  Yueh-Se Ho

IPC分类号： H01L23/06 ,  H01L21/304

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L24/02 ,  H01L24/11 ,  H01L24/17 ,  H01L2221/68354 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

摘要： A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.

摘要翻译： 公开了一种用于在晶片级芯片级封装工艺中进行背对背电连接的方法。 将包含多个半导体芯片的晶片安装在封装基板上。 多个半导体芯片包括暴露背面的一个或多个电极。 去除晶片上的两个或更多个相邻芯片之间的划痕线以形成较宽的间隙。 将导电材料施加到半导体芯片的背面和间隙中。 然后通过在两个或更多个芯片的背侧和侧壁上留下导电材料来切割两个或更多个芯片之间的间隙中的导电材料。 结果，导电材料提供从芯片的背面上的电极到芯片的前侧的电连接。

公开(公告)号：US07811904B2

公开(公告)日：2010-10-12

申请号：US11701561

申请日：2007-01-31

申请人： Tao Feng ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu

发明人： Tao Feng ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu

IPC分类号： H01L21/00

CPC分类号： H01L21/67132 ,  H01L21/288 ,  H01L21/6836 ,  H01L24/02 ,  H01L24/11 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014

摘要： A method of fabricating a semiconductor device employing electroless plating including wafer backside protection during wet processing is disclosed. The method includes the steps of laminating a wafer back side and a frame with a protective tape, applying a protective coating to a peripheral portion of the wafer and an adjoining exposed area of the protective tape, the protective coating, protective tape, and wafer forming a protected wafer assembly, curing the frame-supported protective coating, cutting the protected wafer assembly from the protective tape surrounding the protective coating, wet processing the protected wafer assembly, laminating the protected wafer assembly with a second tape, dicing the wafer, and picking up the die from the protective tape.

摘要翻译： 公开了一种在湿法处理中制造采用化学镀的半导体器件的方法，包括晶片背面保护。 该方法包括以下步骤：将晶片背面和框架与保护带层压，将保护涂层施加到晶片的周边部分以及相邻的保护带的暴露区域，保护涂层，保护带和晶片成形 保护的晶片组件，固化框架支撑的保护涂层，将保护的晶片组件从围绕保护涂层的保护带切割，湿处理受保护的晶片组件，用第二带层压受保护的晶片组件，切割晶片，以及拾取 从保护胶带上取下模具。

公开(公告)号：US20080207094A1

公开(公告)日：2008-08-28

申请号：US11712846

申请日：2007-02-28

申请人： Tao Feng ,  Ming Sun

发明人： Tao Feng ,  Ming Sun

IPC分类号： B24B1/00 ,  B05D1/00 ,  B24B41/06

CPC分类号： B24B7/228 ,  B24B41/06 ,  B28D5/0011 ,  B28D5/0052 ,  H01L24/06 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06181 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/03 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.

摘要翻译： 公开了一种用于超薄晶片背面处理的方法和装置。 该装置包括保持高温研磨和/或切割胶带以形成支撑结构的外圈。 超薄晶片或切片晶片粘附在环内用于晶片背面处理的带子上。 晶片背面处理包括离子注入，退火，蚀刻，溅射和蒸发，而晶片处于支撑结构中。 还公开了支撑结构的替代用途，包括制造具有金属化侧壁的模具。

公开(公告)号：US08361903B2

公开(公告)日：2013-01-29

申请号：US12753426

申请日：2010-04-02

申请人： Tao Feng ,  Ming Sun

发明人： Tao Feng ,  Ming Sun

IPC分类号： H01L21/302

CPC分类号： B24B7/228 ,  B24B41/06 ,  B28D5/0011 ,  B28D5/0052 ,  H01L24/06 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06181 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/03 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.

摘要翻译： 公开了一种用于超薄晶片背面处理的方法和装置。 该装置包括保持高温研磨和/或切割胶带以形成支撑结构的外圈。 超薄晶片或切片晶片粘附在环内用于晶片背面处理的带子上。 晶片背面处理包括离子注入，退火，蚀刻，溅射和蒸发，而晶片处于支撑结构中。 还公开了支撑结构的替代用途，包括制造具有金属化侧壁的模具。

公开(公告)号：US20100221431A1

公开(公告)日：2010-09-02

申请号：US12753426

申请日：2010-04-02

申请人： Tao Feng ,  Ming Sun

发明人： Tao Feng ,  Ming Sun

IPC分类号： B05D3/12 ,  B05D3/06 ,  B05D3/10

CPC分类号： B24B7/228 ,  B24B41/06 ,  B28D5/0011 ,  B28D5/0052 ,  H01L24/06 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06181 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/03 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.

摘要翻译： 公开了一种用于超薄晶片背面处理的方法和装置。 该装置包括保持高温研磨和/或切割胶带以形成支撑结构的外圈。 超薄晶片或切片晶片粘附在环内用于晶片背面处理的带子上。 晶片背面处理包括离子注入，退火，蚀刻，溅射和蒸发，而晶片处于支撑结构中。 还公开了支撑结构的替代用途，包括制造具有金属化侧壁的模具。

公开(公告)号：US07776746B2

公开(公告)日：2010-08-17

申请号：US11712846

申请日：2007-02-28

申请人： Tao Feng ,  Ming Sun

发明人： Tao Feng ,  Ming Sun

IPC分类号： H01L21/302

CPC分类号： B24B7/228 ,  B24B41/06 ,  B28D5/0011 ,  B28D5/0052 ,  H01L24/06 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06181 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/03 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.

摘要翻译： 公开了一种用于超薄晶片背面处理的方法和装置。 该装置包括保持高温研磨和/或切割胶带以形成支撑结构的外圈。 超薄晶片或切片晶片粘附在环内用于晶片背面处理的带子上。 晶片背面处理包括离子注入，退火，蚀刻，溅射和蒸发，而晶片处于支撑结构中。 还公开了支撑结构的替代用途，包括制造具有金属化侧壁的模具。

公开(公告)号：US20090194880A1

公开(公告)日：2009-08-06

申请号：US12023921

申请日：2008-01-31

申请人： Tao Feng ,  Francois Hebert ,  Ming Sun ,  Yueh-Se Ho

发明人： Tao Feng ,  Francois Hebert ,  Ming Sun ,  Yueh-Se Ho

IPC分类号： H01L23/48 ,  H01L21/304

CPC分类号： H01L29/7827 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/81 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/49 ,  H01L29/7802 ,  H01L2224/02371 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

摘要： Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.

摘要翻译： 封装了功率晶圆级芯片级封装（CSP）和制造工艺。 功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，方便用焊膏安装到印刷电路板（PCB）。

公开(公告)号：US08716063B2

公开(公告)日：2014-05-06

申请号：US13007356

申请日：2011-01-14

申请人： Tao Feng ,  François Hébert ,  Ming Sun ,  Yueh-Se Ho

发明人： Tao Feng ,  François Hébert ,  Ming Sun ,  Yueh-Se Ho

IPC分类号： H01L21/00

CPC分类号： H01L29/7827 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/81 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/49 ,  H01L29/7802 ,  H01L2224/02371 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

摘要： Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.

摘要翻译： 封装了功率晶圆级芯片级封装（CSP）和制造工艺。 功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，便于用焊膏安装到印刷电路板（PCB）。

公开(公告)号：US20140076846A1

公开(公告)日：2014-03-20

申请号：US13621289

申请日：2012-09-16

申请人： Tao Feng ,  Ming Sun

发明人： Tao Feng ,  Ming Sun

IPC分类号： B32B38/00

CPC分类号： B32B38/0012 ,  B32B2038/0016 ,  B32B2038/0092 ,  B32B2309/10 ,  B32B2457/14 ,  H01L21/67132 ,  H01L21/6836 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/0556 ,  H01L2224/05568 ,  H01L2224/06183 ,  H01L2224/131 ,  H01L2224/16105 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/17104 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/05552

摘要： A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.

摘要翻译： 公开了一种用于超薄晶片背面处理的方法和装置。 该装置包括保持高温研磨和/或切割胶带以形成支撑结构的外圈。 超薄晶片或切片晶片粘附在环内用于晶片背面处理的带子上。 晶片背面处理包括离子注入，退火，蚀刻，溅射和蒸发，而晶片处于支撑结构中。 还公开了支撑结构的替代用途，包括制造具有金属化侧壁的模具。