-
公开(公告)号:US06818969B2
公开(公告)日:2004-11-16
申请号:US10283365
申请日:2002-10-30
IPC分类号: H01L23495
CPC分类号: H01L23/49838 , H01L21/4832 , H01L23/4824 , H01L23/49541 , H01L23/49562 , H01L23/49844 , H01L23/66 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/0605 , H01L2223/6644 , H01L2223/6688 , H01L2224/05554 , H01L2224/32057 , H01L2224/32225 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48463 , H01L2224/49171 , H01L2224/73265 , H01L2224/83385 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/10161 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/1306 , H01L2924/13063 , H01L2924/14 , H01L2924/1423 , H01L2924/15313 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H03K17/002 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要: A semiconductor device includes four input terminals, four leads extending from the corresponding input terminals and a semiconductor chip that has a first circuit and a second circuit and is mounted on one of the leads. The lead having the semiconductor chip thereon bends in a plane of the substrate so that an end portion and a mid portion of the lead are exposed on one side of the semiconductor chip. One of the input electrode pads of the first circuit is connected to the end portion of the lead by a bonding wire. The end portion of the lead is on the opposite side of the mid portion of the lead with respect to one of the leads that is connected to one of the input electrode pads of the second circuit by a bonding wire. This configuration achieves a crossing wiring structure within the packaging. By changing the connection of bonding wires, the crossing wiring structure is easily undone.
摘要翻译: 半导体器件包括四个输入端子,从相应的输入端子延伸的四个引线和具有第一电路和第二电路并且安装在引线之一上的半导体芯片。 其上具有半导体芯片的引线在基板的平面中弯曲,使得引线的端部和中间部分在半导体芯片的一侧露出。 第一电路的输入电极焊盘之一通过接合线连接到引线的端部。 引线的端部相对于通过接合线连接到第二电路的一个输入电极焊盘的引线之一位于引线的中间部分的相对侧。 该配置实现了包装内的交叉布线结构。 通过改变接合线的连接,交叉布线结构容易被取消。
-
公开(公告)号:US06833616B2
公开(公告)日:2004-12-21
申请号:US10310139
申请日:2002-12-05
IPC分类号: H05K111
CPC分类号: H01L23/49838 , H01L23/552 , H01L23/66 , H01L24/48 , H01L24/49 , H01L27/0605 , H01L2224/05554 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01031 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/07802 , H01L2924/09701 , H01L2924/10161 , H01L2924/10329 , H01L2924/1306 , H01L2924/13063 , H01L2924/14 , H01L2924/1423 , H01L2924/15173 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要: A semiconductor chip is mounted on a wiring board that has a two-layer lead structure. One of the leads used for receiving input signals is disposed on the lower layer and runs underneath the semiconductor chip forming an U-shaped wiring line while other leads are disposed on the upper layer. Because one of the upper layer leads for receiving input signals is disposed in the U-shaped pocket of the U-shaped wiring line of the lower layer, the relative positioning of corresponding terminals can be changed into a reversal of the positioning of the electrode pads of the chip connected to the terminals. Furthermore, one of the upper layer lead for receiving control signals is placed between the chip and the lower layer lead underneath the chip to prevent high frequency signal interference.
摘要翻译: 半导体芯片安装在具有双层引线结构的布线板上。 用于接收输入信号的引线之一被布置在下层上并且在形成U形布线的半导体芯片的下方延伸,而在上层设置其它引线。 由于用于接收输入信号的上层引线之一设置在下层的U形布线的U形槽中,所以相应端子的相对定位可以改变为电极焊盘的定位的反转 的芯片连接到终端。 此外,用于接收控制信号的上层引线之一被放置在芯片和芯片下方的下层引线之间,以防止高频信号干扰。
-
公开(公告)号:US06833608B2
公开(公告)日:2004-12-21
申请号:US10294912
申请日:2002-11-15
IPC分类号: H01L23495
CPC分类号: H01L24/32 , H01L23/49562 , H01L23/49844 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L27/0605 , H01L2224/05554 , H01L2224/32057 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48464 , H01L2224/49171 , H01L2224/73265 , H01L2224/83385 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01039 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/14 , H01L2924/1423 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00012 , H01L2924/00 , H01L2924/01026 , H01L2924/01032 , H01L2224/45099
摘要: Two different switches with two different signal input schemes are fabricated by mounting the same semiconductor chip on the same lead pattern. Two of the leads of the lead pattern provides space enough for wire-bonding connection to corresponding electrode pads on the semiconductor chip at both ends of the semiconductor chip. Because each of electrode pads can be connected to the corresponding lead at either end of the semiconductor chip, two sets of bonding wire connection between the leads and the electrode pads provides two different switches with two different signal inputs scheme.
摘要翻译: 通过将相同的半导体芯片安装在相同的引线图案上来制造具有两个不同信号输入方案的两个不同的开关。 引线图案的两个引线提供足够的空间,用于与半导体芯片两端的半导体芯片上的相应电极焊盘的引线接合连接。 因为每个电极焊盘可以连接到半导体芯片的任一端处的对应引线,所以引线和电极焊盘之间的两组接合线连接提供具有两种不同信号输入方案的两个不同的开关。
-
公开(公告)号:US07732868B2
公开(公告)日:2010-06-08
申请号:US10521941
申请日:2002-11-28
IPC分类号: H01L29/812
CPC分类号: H01L29/812 , H01L27/0248 , H01L27/0255 , H01L29/808
摘要: A protecting element, comprising a first n+-type region, an insulating region, and a second n+-type region, is connected in parallel between two terminals of an FET. Since discharge across the first and second n+ regions is enabled, electrostatic energy that reaches the operating region of the FET can be attenuated without increasing the parasitic capacitance.
摘要翻译: 在FET的两个端子之间并联连接包括第一n +型区域,绝缘区域和第二n +型区域的保护元件。 由于能够使第一和第二n +区域的放电得以实现,所以到达FET工作区域的静电能量可以衰减而不增加寄生电容。
-
公开(公告)号:US07358788B2
公开(公告)日:2008-04-15
申请号:US11412077
申请日:2006-04-27
IPC分类号: H03K5/08
CPC分类号: H01L29/7785 , H01L21/8252 , H01L27/0266 , H01L27/0605
摘要: Protecting elements are respectively connected between a control terminal Ctl and a ground terminal GND of a logic circuit L, between a point Cp and a ground terminal GND, and between a power supply terminal VDD and a ground terminal GND thereof. With this, an E-FET, constituting an inverter 70, and capacitors Ci and Cr can be protected from electrostatic breakdown due to external static electricity. Since the protecting element can be constituted by requisite components for the logic circuit, an additional step or structure is not especially required to provide the protecting element.
摘要翻译: 保护元件分别连接在控制端子Ct1和逻辑电路L的接地端子GND之间,位于点Cp和接地端子GND之间,以及电源端子V DD端子和接地端子 GND。 由此,可以防止构成反相器70的电子FET,电容器Ci,Cr由于外部静电而受到静电破坏。 由于保护元件可以由用于逻辑电路的必需部件构成,所以不需要额外的步骤或结构来提供保护元件。
-
公开(公告)号:US20060289963A1
公开(公告)日:2006-12-28
申请号:US11442600
申请日:2006-05-30
申请人: Tetsuro Asano , Yuichi Kusaka , Mikito Sakakibara
发明人: Tetsuro Asano , Yuichi Kusaka , Mikito Sakakibara
IPC分类号: H01L29/00
CPC分类号: H01L27/0605 , H01L29/402 , H01L29/737 , H01L29/778 , H01L29/808 , H01L29/812
摘要: A separation element formed of one of a conduction region and a metal layer is placed between two elements in proximity to each other. The separation element is connected to a high resistance element and to a direct current terminal pad. A connection route extending from the direct current terminal pad to the separation element is a route in which a potential does not vibrate with high frequency. This results in a placement of a high frequency GND potential between the two elements, at least one of which is subjected to transmitting the high frequency signals, whereby leak of the high frequency signals can be prevented between the two elements.
摘要翻译: 由导电区域和金属层之一形成的分离元件彼此靠近放置在两个元件之间。 分离元件连接到高电阻元件和直流端子焊盘。 从直流端子焊盘延伸到分离元件的连接路径是电位不以高频率振动的路径。 这导致在两个元件之间放置高频GND电位,其中至少一个被传送高频信号,从而可以防止两个元件之间的高频信号泄漏。
-
公开(公告)号:US20050179106A1
公开(公告)日:2005-08-18
申请号:US11103598
申请日:2005-04-12
申请人: Tetsuro Asano , Katsuaki Onoda , Yoshibumi Nakajima , Shigeyuki Murai , Hisaaki Tominaga , Koichi Hirata , Mikito Sakakibara , Hidetoshi Ishihara
发明人: Tetsuro Asano , Katsuaki Onoda , Yoshibumi Nakajima , Shigeyuki Murai , Hisaaki Tominaga , Koichi Hirata , Mikito Sakakibara , Hidetoshi Ishihara
IPC分类号: H01L21/329 , H01L29/872 , H01L27/095
CPC分类号: H01L29/66143 , H01L29/872
摘要: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.
摘要翻译: 肖特基势垒二极管在GaAs衬底的工作区域和围绕肖特基电极的欧姆电极上形成肖特基电极。 欧姆电极直接设置在形成在基板上的杂质注入区域上。 氮化膜将欧姆电极与穿过欧姆电极的肖特基电极连接的布线层绝缘。 该器件的平面结构不包括传统的聚酰亚胺层,因此具有比常规器件更好的高频特性。
-
公开(公告)号:US06891267B2
公开(公告)日:2005-05-10
申请号:US10414492
申请日:2003-04-16
申请人: Tetsuro Asano , Mikito Sakakibara
发明人: Tetsuro Asano , Mikito Sakakibara
IPC分类号: H01L21/822 , H01L21/338 , H01L23/482 , H01L23/485 , H01L23/528 , H01L23/552 , H01L23/66 , H01L27/04 , H01L27/06 , H01L27/095 , H01L29/812 , H03K17/693 , H01L23/34
CPC分类号: H01L24/05 , H01L23/4824 , H01L23/552 , H01L23/66 , H01L24/06 , H01L24/48 , H01L27/0605 , H01L2224/04042 , H01L2224/05552 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/05644 , H01L2224/05666 , H01L2224/05669 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/85201 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01031 , H01L2924/01037 , H01L2924/01078 , H01L2924/01079 , H01L2924/01088 , H01L2924/10161 , H01L2924/10329 , H01L2924/12032 , H01L2924/1306 , H01L2924/13063 , H01L2924/14 , H01L2924/1423 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要: A semiconductor switching circuit device includes a field effect transistor having a source electrode, a gate electrode and a drain electrode, a first electrode pad connected to the source electrode or the drain electrode, and a second electrode pad connected to the source electrode or the drain electrode which is not connected to the first electrode pad. The device also includes a third electrode pad receiving a DC voltage and applying the DC voltage to the field effect transistor, a first insulating layer covering the field effect transistor, a metal layer disposed above the first insulating layer and connected to the third electrode pad, and a second insulating layer disposed on the metal layer. The third electrode pad may be a control terminal pad, a ground terminal pad or a terminal pad receiving a constant DC power voltage. The metal layer may be a flat sheet, a lattice or a comb-like structure.
摘要翻译: 一种半导体开关电路装置,包括具有源电极,栅电极和漏电极的场效应晶体管,连接到源电极或漏极的第一电极焊盘和连接到源电极或漏极的第二电极焊盘 电极,其未连接到第一电极焊盘。 该装置还包括:接收DC电压并将DC电压施加到场效应晶体管的第三电极焊盘,覆盖场效应晶体管的第一绝缘层,设置在第一绝缘层上方并连接到第三电极焊盘的金属层, 以及设置在所述金属层上的第二绝缘层。 第三电极焊盘可以是控制端子焊盘,接地端子焊盘或接收恒定DC电源电压的端子焊盘。 金属层可以是平板状,格子状或梳状结构。
-
公开(公告)号:US06573529B2
公开(公告)日:2003-06-03
申请号:US10152880
申请日:2002-05-24
IPC分类号: H01L2906
CPC分类号: H01L27/0605
摘要: A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 &mgr;m and a signal receiving FET has a gate width of 400 &mgr;m. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.
-
公开(公告)号:US07701032B2
公开(公告)日:2010-04-20
申请号:US11442600
申请日:2006-05-30
申请人: Tetsuro Asano , Yuichi Kusaka , Mikito Sakakibara
发明人: Tetsuro Asano , Yuichi Kusaka , Mikito Sakakibara
IPC分类号: H01L29/80
CPC分类号: H01L27/0605 , H01L29/402 , H01L29/737 , H01L29/778 , H01L29/808 , H01L29/812
摘要: A separation element formed of one of a conduction region and a metal layer is placed between two elements in proximity to each other. The separation element is connected to a high resistance element and to a direct current terminal pad. A connection route extending from the direct current terminal pad to the separation element is a route in which a potential does not vibrate with high frequency. This results in a placement of a high frequency GND potential between the two elements, at least one of which is subjected to transmitting the high frequency signals, whereby leak of the high frequency signals can be prevented between the two elements.
摘要翻译: 由导电区域和金属层之一形成的分离元件彼此靠近放置在两个元件之间。 分离元件连接到高电阻元件和直流端子焊盘。 从直流端子焊盘延伸到分离元件的连接路径是电位不以高频率振动的路径。 这导致在两个元件之间放置高频GND电位,其中至少一个被传送高频信号,从而可以防止两个元件之间的高频信号泄漏。
-
-
-
-
-
-
-
-
-