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32 条记录 (耗时 0.026 秒)

    Memory control circuit, memory device, and microcomputer
    1.
    发明授权
    Memory control circuit, memory device, and microcomputer 有权
    存储器控制电路，存储器件和微计算机

    公开(公告)号：US07174435B2

    公开(公告)日：2007-02-06

    申请号：US10715366

    申请日：2003-11-19

    申请人： Tetsuya Yoshida ,  Yoshihiko Koike ,  Masayoshi Kusumoto

    发明人： Tetsuya Yoshida ,  Yoshihiko Koike ,  Masayoshi Kusumoto

    IPC分类号： G06F12/16

    CPC分类号： G06F11/00

    摘要： First and second latch circuits store “0” and “1”, respectively, by reset. An output signal from the first latch circuit is input to the second latch circuit. Register setting data is input to the first latch circuit via a first gate that allows an input signal to pass through when the output signal from the second latch circuit is “1”, and outputs “0” when the output signal from the second latch circuit is “0”. A write signal is supplied to a memory via a second gate that allows the input signal to pass through only when the output signal from the first latch circuit is “1”. When the register setting data indicates “0”, the output signals from both the first and the second latch circuits become “0”, and until being reset, the write error protect state is maintained.

    摘要翻译： 第一和第二锁存电路通过复位分别存储“0”和“1”。 来自第一锁存电路的输出信号被输入到第二锁存电路。 当第二锁存电路的输出信号为“1”时，寄存器设定数据通过允许输入信号通过的第一栅极输入到第一锁存电路，当来自第二锁存电路的输出信号时，输出“0” 是“0”。 经由第二栅极将写入信号提供给存储器，只有当来自第一锁存电路的输出信号为“1”时，允许输入信号通过。 当寄存器设置数据指示为“0”时，来自第一和第二锁存电路的输出信号变为“0”，直到被复位为止，保持写入错误保护状态。

    Semiconductor device
    2.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060049400A1

    公开(公告)日：2006-03-09

    申请号：US11043336

    申请日：2005-01-27

    申请人： Tetsuya Yoshida ,  Yoshihiko Koike

    发明人： Tetsuya Yoshida ,  Yoshihiko Koike

    IPC分类号： H01L23/58

    CPC分类号： H01L23/544 ,  H01L27/11213 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A first wiring part in a first wiring layer is a starting terminal that is connected to a ground potential. The first wiring part and a second wiring part in a second wiring layer are connected by a first connecting part. The second wiring part and a third wiring part in a third wiring layer are connected by a second connecting part. A fourth wiring part continuously connected with the third wiring part and a fifth wiring part in the second wiring layer are connected by a third connecting part. The fifth wiring part and a sixth wiring part in the first wiring layer are connected by a fourth connecting part. A conducting path that is continuously connected from the starting terminal to an output end is formed by connecting a mound-shaped conducting path thus formed.

    摘要翻译： 第一布线层中的第一布线部分是连接到地电位的起始端。 第一布线部分和第二布线层中的第二布线部分通过第一连接部连接。 第二布线部分和第三布线层中的第三布线部分通过第二连接部连接。 与第三布线部连续地连接的第四布线部和第二布线层中的第五布线部通过第三连接部连接。 第一布线层中的第五布线部分和第六布线部分由第四连接部分连接。 从起动端子连续地连接到输出端的导电路径通过连接如此形成的堆焊状导电路径而形成。

    Marginless status determination circuit
    3.
    发明授权
    Marginless status determination circuit 失效
    无边缘状态确定电路

    公开(公告)号：US07454649B2

    公开(公告)日：2008-11-18

    申请号：US11238957

    申请日：2005-09-30

    申请人： Kenji Yoshida ,  Yoshihiko Koike ,  Tetsuya Yoshida

    发明人： Kenji Yoshida ,  Yoshihiko Koike ,  Tetsuya Yoshida

    IPC分类号： G06F1/00

    CPC分类号： G01R31/31727

    摘要： By including a unit for storing data to be determined, a unit for delaying the data, a unit for storing the output of the delay unit, and a unit for comparing the storage contents of the data before the delay with the storage contents of the data after the delay, and outputting a marginless status detection signal when they are different, the presence/absence of a margin is monitored regardless of ambient conditions by using an output marginless status detection signal as a switch control signal for a clock switch circuit, thereby operating electronic equipment without changing a frequency of a clock signal up to the critical condition.

    摘要翻译： 通过包括用于存储要确定的数据的单元，用于延迟数据的单元，用于存储延迟单元的输出的单元，以及用于将延迟之前的数据的存储内容与数据的存储内容进行比较的单元 在延迟之后，并且当它们不同时输出无余位状态检测信号，通过使用输出无余位状态检测信号作为时钟切换电路的开关控制信号，无论环境条件如何，都监视是否存在余量，从而操作 电子设备，而不改变时钟信号的频率，直到临界状态。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US07091518B2

    公开(公告)日：2006-08-15

    申请号：US11043336

    申请日：2005-01-27

    申请人： Tetsuya Yoshida ,  Yoshihiko Koike

    发明人： Tetsuya Yoshida ,  Yoshihiko Koike

    IPC分类号： H01L23/58

    CPC分类号： H01L23/544 ,  H01L27/11213 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A first wiring part in a first wiring layer is a starting terminal that is connected to a ground potential. The first wiring part and a second wiring part in a second wiring layer are connected by a first connecting part. The second wiring part and a third wiring part in a third wiring layer are connected by a second connecting part. A fourth wiring part continuously connected with the third wiring part and a fifth wiring part in the second wiring layer are connected by a third connecting part. The fifth wiring part and a sixth wiring part in the first wiring layer are connected by a fourth connecting part. A conducting path that is continuously connected from the starting terminal to an output end is formed by connecting a mound-shaped conducting path thus formed.

    Marginless status determination circuit
    5.
    发明申请
    Marginless status determination circuit 失效
    无边缘状态确定电路

    公开(公告)号：US20060208745A1

    公开(公告)日：2006-09-21

    申请号：US11238957

    申请日：2005-09-30

    申请人： Kenji Yoshida ,  Yoshihiko Koike ,  Tetsuya Yoshida

    发明人： Kenji Yoshida ,  Yoshihiko Koike ,  Tetsuya Yoshida

    IPC分类号： G01R27/28

    CPC分类号： G01R31/31727

    摘要： By including a unit for storing data to be determined, a unit for delaying the data, a unit for storing the output of the delay unit, and a unit for comparing the storage contents of the data before the delay with the storage contents of the data after the delay, and outputting a marginless status detection signal when they are different, the presence/absence of a margin is monitored regardless of ambient conditions by using an output marginless status detection signal as a switch control signal for a clock switch circuit, thereby operating electronic equipment without changing a frequency of a clock signal up to the critical condition.

    摘要翻译： 通过包括用于存储要确定的数据的单元，用于延迟数据的单元，用于存储延迟单元的输出的单元，以及用于将延迟之前的数据的存储内容与数据的存储内容进行比较的单元 在延迟之后，并且当它们不同时输出无余位状态检测信号，通过使用输出无余位状态检测信号作为时钟切换电路的开关控制信号，无论环境条件如何，都监视是否存在余量，从而操作 电子设备，而不改变时钟信号的频率，直到临界状态。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US06621328B2

    公开(公告)日：2003-09-16

    申请号：US10096426

    申请日：2002-03-13

    申请人： Yoshihiko Koike ,  Shuji Yoshida ,  Tetsuya Yoshida

    发明人： Yoshihiko Koike ,  Shuji Yoshida ,  Tetsuya Yoshida

    IPC分类号： G05F110

    CPC分类号： G06F1/26

    摘要： A semiconductor device that prevents malfunction in an external circuit by preventing an indefinite signal from being output at the time of power being applied. A processing circuit is supplied with an internal power supply voltage from an internal power supply voltage generating circuit and performs a predetermined process. An output circuit outputs the result of processing by the processing circuit. When the supply of an external power supply voltage is begun, a control circuit exercises control so that output from the output circuit will be kept in a predetermined state. A supply circuit supplies an external power supply voltage to the control circuit.

    Semiconductor device including an external oscillation circuit
    7.
    发明授权
    Semiconductor device including an external oscillation circuit 有权
    包括外部振荡电路的半导体装置

    公开(公告)号：US07135939B2

    公开(公告)日：2006-11-14

    申请号：US10856816

    申请日：2004-06-01

    申请人： Yoshihiko Koike ,  Shuji Yoshida

    发明人： Yoshihiko Koike ,  Shuji Yoshida

    IPC分类号： H03L3/00 ,  H03B5/00 ,  H03B5/06 ,  H03B5/36

    CPC分类号： G06F1/04

    摘要： A semiconductor device includes an external oscillation circuit connected to an external resonator, a self-exciting oscillation circuit, and an oscillation clock monitoring circuit, the oscillation clock monitoring circuit monitors an oscillation state of the external resonator using a clock signal generated by the self-exciting oscillation circuit, and when judged that the oscillation state has been stabilized, the terminating signal of the waiting time for stabilization of oscillation is outputted to terminate the waiting time for stabilization of oscillation of a microcomputer forcedly.

    摘要翻译： 半导体器件包括连接到外部谐振器的外部振荡电路，自激振荡电路和振荡时钟监视电路，振荡时钟监视电路使用由自激振荡器产生的时钟信号来监视外部谐振器的振荡状态， 激励振荡电路，并且当判断振荡状态已经稳定时，输出用于稳定振荡的等待时间的终止信号，以终止用于稳定微型计算机的振荡的等待时间。

    Semiconductor module and inverter device
    9.
    发明授权
    Semiconductor module and inverter device 失效
    半导体模块和逆变器

    公开(公告)号：US06441317B1

    公开(公告)日：2002-08-27

    申请号：US09654085

    申请日：2000-09-01

    申请人： Akira Tanaka ,  Ryuichi Saito ,  Tadao Kushima ,  Yoshihiko Koike ,  Hideo Shimizu ,  Shigeharu Nonoyama

    发明人： Akira Tanaka ,  Ryuichi Saito ,  Tadao Kushima ,  Yoshihiko Koike ,  Hideo Shimizu ,  Shigeharu Nonoyama

    IPC分类号： H05K116

    CPC分类号： H01L25/072 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01019 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/30107 ,  H01L2924/00

    摘要： In a semiconductor module comprising, a semiconductor element, an electrically insulating base having an outer surface to be connected to an electrically grounded surface, and an inner surface on which the semiconductor element is arranged, an electrically insulating cover covering the semiconductor element on the inner surface, and first and second electrically conductive members each of which is connected to the semiconductor element and extends to the exterior of the semiconductor module through the electrically insulating cover, a part of each of the first and second electrically conductive members on the exterior of the semiconductor module is arranged away from the outer surface to electrically isolate the part of the each of the first and second electrically conductive members from the electrically grounded surface.

    摘要翻译： 在半导体模块中，包括半导体元件，具有要连接到电接地表面的外表面的电绝缘基底和布置有半导体元件的内表面，覆盖在内部的半导体元件的电绝缘盖 表面以及第一和第二导电构件，每个导电构件连接到半导体元件并且通过电绝缘盖延伸到半导体模块的外部，第一和第二导电构件中的每一个的外部的一部分 半导体模块远离外表面布置，以将第一和第二导电构件中的每一个的一部分与电接地表面电隔离。