公开(公告)号：US20050218414A1

公开(公告)日：2005-10-06

申请号：US10812416

申请日：2004-03-30

申请人： Tetsuzo Ueda ,  Tsunenobu Kimoto ,  Hiroyuki Matsunami ,  Jun Suda ,  Norio Onojima

发明人： Tetsuzo Ueda ,  Tsunenobu Kimoto ,  Hiroyuki Matsunami ,  Jun Suda ,  Norio Onojima

IPC分类号： H01L29/26 ,  H01L21/02 ,  H01L21/20 ,  H01L21/338 ,  H01L29/778 ,  H01L29/812 ,  H01L33/18 ,  H01L33/32 ,  H01S5/323 ,  H01L33/00

CPC分类号： H01L21/02082 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/18 ,  H01L33/32

摘要： 4H-InGaAlN alloy based optoelectronic and electronic devices on non-polar face are formed on 4H-AlN or 4H-AlGaN on (11-20) a-face 4H-SiC substrates. Typically, non polar 4H-AlN is grown on 4H-SiC (11-20) by molecular beam epitaxy (MBE). Subsequently, III-V nitride device layers are grown by metal organic chemical vapor deposition (MOCVD) with 4H-polytype for all of the layers. The non-polar device does not contain any built-in electric field due to the spontaneous and piezoelectric polarization. The optoelectonic devices on the non-polar face exhibits higher emission efficiency with shorter emission wavelength because the electrons and holes are not spatially separated in the quantum well. Vertical device configuration for lasers and light emitting diodes(LEDs) using conductive 4H-AlGaN interlayer on conductive 4H-SiC substrates makes the chip size and series resistance smaller. The elimination of such electric field also improves the performance of high speed and high power transistors. The details of the epitaxial growth s and the processing procedures for the non-polar III-V nitride devices on the non-polar SiC substrates are also disclosed.

摘要翻译： 在（11-20）a面4H-SiC衬底上的4H-AlN或4H-AlGaN上形成4H-InGaAlN合金基非极性面上的光电子和电子器件。 通常，非极性4H-AlN通过分子束外延（MBE）在4H-SiC（11-20）上生长。 随后，通过用于所有层的4H-多型金属有机化学气相沉积（MOCVD）生长III-V族氮化物器件层。 由于自发和压电极化，非极性器件不包含任何内置的电场。 由于电子和空穴在量子阱中空间不分开，非极性面上的光电子器件表现出更高的发射效率，发射波长更短。 在导电4H-SiC衬底上使用导电4H-AlGaN夹层的激光器和发光二极管（LED）的垂直器件配置使芯片尺寸和串联电阻更小。 这种电场的消除也提高了高速和高功率晶体管的性能。 还公开了非极性SiC衬底上的非极性III-V族氮化物器件的外延生长细节和处理步骤。

公开(公告)号：US08872227B2

公开(公告)日：2014-10-28

申请号：US13402631

申请日：2012-02-22

申请人： Hidekazu Umeda ,  Yoshiharu Anda ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Hidekazu Umeda ,  Yoshiharu Anda ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/417 ,  H01L29/20

CPC分类号： H01L29/2003 ,  H01L29/1066 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/861

摘要： A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.

摘要翻译： 氮化物半导体器件包括半导体衬底和形成在半导体衬底上的氮化物半导体层。 半导体衬底包括正常区域和围绕法线区域的界面电流阻挡区域。 氮化物半导体层包括元件区域和围绕元件区域的隔离区域。 元件区域形成在正常区域上。 界面电流阻挡区域含有杂质，并且在氮化物半导体层和半导体衬底之间的界面处产生的载流子形成势垒。

公开(公告)号：US08779438B2

公开(公告)日：2014-07-15

申请号：US13569014

申请日：2012-08-07

申请人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L29/15 ,  H01L31/0256 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC分类号： H01L29/7786 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

摘要翻译： 依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。 栅电极与重掺杂的p型GaN层形成欧姆接触。 源电极和漏电极设置在未掺杂的AlGaN层上。 通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

公开(公告)号：US08742467B2

公开(公告)日：2014-06-03

申请号：US13613724

申请日：2012-09-13

申请人： Tatsuo Morita ,  Daisuke Ueda ,  Yasuhiro Uemoto ,  Tetsuzo Ueda

发明人： Tatsuo Morita ,  Daisuke Ueda ,  Yasuhiro Uemoto ,  Tetsuzo Ueda

IPC分类号： H01L29/772 ,  H01L29/778

CPC分类号： H01L29/7787 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003

摘要： A bidirectional switching device includes a semiconductor multilayer structure made of a nitride semiconductor, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor multilayer structure, and a first gate electrode and a second gate electrode. The first gate electrode is covered with a first shield electrode having a potential substantially equal to that of the first ohmic electrode. The second gate electrode is covered with the second shield electrode having a potential substantially equal to that of the second ohmic electrode. An end of the first shield electrode is positioned between the first gate electrode and the second gate electrode, and an end of the second shield electrode is positioned between the second gate electrode and the first gate electrode.

摘要翻译： 双向开关器件包括由半导体多层结构上形成的由氮化物半导体，第一欧姆电极和第二欧姆电极构成的半导体多层结构以及第一栅电极和第二栅电极。 第一栅电极被第一屏蔽电极覆盖，该第一屏蔽电极的电位基本上等于第一欧姆电极的电位。 第二栅电极被第二屏蔽电极覆盖，其电位基本上等于第二欧姆电极的电位。 第一屏蔽电极的端部位于第一栅极电极和第二栅极电极之间，第二屏蔽电极的端部位于第二栅极电极和第一栅极电极之间。

公开(公告)号：US08569797B2

公开(公告)日：2013-10-29

申请号：US13185818

申请日：2011-07-19

申请人： Hidekazu Umeda ,  Masahiro Hikita ,  Tetsuzo Ueda

发明人： Hidekazu Umeda ,  Masahiro Hikita ,  Tetsuzo Ueda

IPC分类号： H01L29/80

CPC分类号： H01L29/7783 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

摘要： A field-effect transistor includes a first semiconductor layer formed on a substrate, and a second semiconductor layer. The first semiconductor layer has a containing region provided as an isolation region which contains non-conductive impurities, and a non-containing region which contains no non-conductive impurities. A first region is defined by a vicinity of a portion of the interface between the containing region and the non-containing region, the portion of the interface being below a gate electrode, the vicinity including the portion of the interface and being included in the containing region. The second semiconductor layer includes a second region which is located directly above the first region. The concentration of the non-conductive impurities of the second region is lower than that of the first region.

摘要翻译： 场效应晶体管包括形成在衬底上的第一半导体层和第二半导体层。 第一半导体层具有设置为包含非导电杂质的隔离区域的含有区域和不含非导电杂质的非含有区域。 第一区域由容纳区域和非含有区域之间的界面的一部分的附近限定，界面的部分在栅电极下方，包括界面部分的附近包含在包含 地区。 第二半导体层包括位于第一区域正上方的第二区域。 第二区域的非导电性杂质的浓度低于第一区域的浓度。

公开(公告)号：US08344423B2

公开(公告)日：2013-01-01

申请号：US13360275

申请日：2012-01-27

申请人： Yasuhiro Uemoto ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Yasuhiro Uemoto ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L29/66

CPC分类号： H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/7783

摘要： A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.

摘要翻译： 氮化物半导体器件包括：第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更宽的带隙的第二氮化物半导体层; 以及形成在所述第二氮化物半导体层上的第三氮化物半导体层。 位于栅电极下方的第三氮化物半导体层的区域形成有具有p型导电性的控制区域，以及位于栅电极与源电极和漏极之间的第三氮化物半导体层的区域 形成有具有比控制区域更高的电阻的高电阻区域。

公开(公告)号：US20120299011A1

公开(公告)日：2012-11-29

申请号：US13569014

申请日：2012-08-07

申请人： Masahiro HIKITA ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro HIKITA ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L29/778

CPC分类号： H01L29/7786 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

摘要翻译： 依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。 栅电极与重掺杂的p型GaN层形成欧姆接触。 源电极和漏电极设置在未掺杂的AlGaN层上。 通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

公开(公告)号：US20120119261A1

公开(公告)日：2012-05-17

申请号：US13356156

申请日：2012-01-23

申请人： Hidekazu UMEDA ,  Tetsuzo Ueda

发明人： Hidekazu UMEDA ,  Tetsuzo Ueda

IPC分类号： H01L29/778

CPC分类号： H01L29/7786 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462

摘要： A semiconductor device includes: a substrate 101, a first nitride semiconductor layer 104S which includes a plurality of nitride semiconductor layers formed on the substrate 101, and has a channel region; a second semiconductor layer 105 which is formed on the first nitride semiconductor layer 104S, and has a conductivity type opposite a conductivity type of the channel region; a conductive layer which is in contact with the second semiconductor layer 105, and includes a metal layer 107 or a high carrier concentration semiconductor layer having a carrier concentration of 1×1018 cm−3 or higher; an insulating layer 110 formed on the conductive layer; a gate electrode 111 formed on the insulating layer 110; and a source electrode 108 and a drain electrode 109 formed to laterally sandwich the second semiconductor layer 105.

摘要翻译： 半导体器件包括：衬底101，包括形成在衬底101上的多个氮化物半导体层的第一氮化物半导体层104S，并具有沟道区; 第二半导体层105，其形成在第一氮化物半导体层104S上，并且具有与沟道区的导电类型相反的导电类型; 与第二半导体层105接触的导体层，具有载流子浓度为1×1018 cm -3以上的金属层107或高载流子浓度半导体层; 形成在导电层上的绝缘层110; 形成在绝缘层110上的栅电极111; 以及形成为横向夹持第二半导体层105的源电极108和漏电极109。

公开(公告)号：US20110211607A1

公开(公告)日：2011-09-01

申请号：US13105337

申请日：2011-05-11

申请人： Toshiyuki Takizawa ,  Tetsuzo Ueda

发明人： Toshiyuki Takizawa ,  Tetsuzo Ueda

IPC分类号： H01S5/34 ,  H01L33/02

CPC分类号： H01L21/0262 ,  B82Y20/00 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/02636 ,  H01L33/16 ,  H01L33/24 ,  H01L33/32 ,  H01S5/2009 ,  H01S5/2237 ,  H01S5/3202 ,  H01S5/3216 ,  H01S5/34333 ,  H01S2304/04

摘要： An object of the present invention is to provide a nitride semiconductor device which shifts a luminescence wavelength toward a longer wavelength side without decreasing luminescence efficiency, and the nitride semiconductor device according to an implementation of the present invention includes: a GaN layer having a (0001) plane and a plane other than the (0001) plane; and an InGaN layer which contacts the GaN layer and includes indium, and the InGaN layer has a higher indium composition ratio in a portion that contacts the plane other than the (0001) plane than in a portion that contacts the (0001) plane.

摘要翻译： 本发明的目的是提供一种氮化物半导体器件，其将发光波长向较长波长侧移动而不降低发光效率，并且根据本发明的实施方式的氮化物半导体器件包括：具有（0001 ）面和除（0001）面之外的平面; 以及与GaN层接触并包含铟的InGaN层，并且InGaN层在与（0001）面以外的平面接触的部分中的铟成分比在与（0001）面接触的部分相比更高。

公开(公告)号：US20110175142A1

公开(公告)日：2011-07-21

申请号：US13120382

申请日：2009-08-26

申请人： Naohiro Tsurumi ,  Satoshi Nakazawa ,  Tetsuzo Ueda

发明人： Naohiro Tsurumi ,  Satoshi Nakazawa ,  Tetsuzo Ueda

IPC分类号： H01L29/80

CPC分类号： H01L29/1075 ,  H01L23/481 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/4175 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nitride semiconductor device includes a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer, and having a wider bad gap than the first nitride semiconductor layer; a source electrode, a drain electrode, and a gate electrode, which are formed on the second nitride semiconductor layer; a high resistive layer formed lower than the first nitride semiconductor layer; a conductive layer formed under and in contact with the high resistive layer; a lower insulating layer formed under the conductive layer; and a bias terminal electrically connected to the conductive layer.

摘要翻译： 氮化物半导体器件包括第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更宽的不良间隙的第二氮化物半导体层; 源电极，漏电极和栅电极，形成在第二氮化物半导体层上; 形成为低于第一氮化物半导体层的高电阻层; 形成在所述高电阻层之下并与所述高电阻层接触的导电层; 形成在导电层下面的下绝缘层; 以及电连接到所述导电层的偏置端子。