公开(公告)号：US20090195948A1

公开(公告)日：2009-08-06

申请号：US12162599

申请日：2007-01-31

申请人： Edvard Kalvesten ,  Tomas Bauer ,  Thorbjorn Ebefors

发明人： Edvard Kalvesten ,  Tomas Bauer ,  Thorbjorn Ebefors

IPC分类号： H02H9/00 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L21/322 ,  H01L29/861 ,  H01L31/00

CPC分类号： H01L23/49827 ,  H01L21/76898 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections. Also there is provided a wafer substrate for making integrated electronic circuits and/or components, comprising a low resistivity silicon base (110) having a high resistivity top layer (122) suitable for semiconductor engineering, characterized by having low resistivity wafer through connections (140).

摘要翻译： 本发明涉及一种通过连接（140; 192）制造具有电晶片的用于半导体工程的起始衬底晶片的方法。 它包括提供具有前侧和后侧的具有低电阻率硅基底和前侧的高电阻率材料层的晶片（110,150）。 在晶片上，在高电阻率材料层中存在低电阻率材料岛。 这些岛与硅基材料接触。 沟槽从晶片的背面蚀刻，但并不全部穿过晶片，以提供通过连接（140; 192）限定晶片的绝缘外壳。 沟槽填充有绝缘材料。 然后研磨晶片的正面以露出绝缘材料，以通过连接产生晶片。 还提供了一种用于制造集成电子电路和/或部件的晶片基板，包括具有适用于半导体工程的高电阻率顶层（122）的低电阻率硅基底（110），其特征在于具有低电阻率晶圆连接（140 ）。

公开(公告)号：US20100053922A1

公开(公告)日：2010-03-04

申请号：US12523811

申请日：2008-01-25

申请人： Thorbjorn Ebefors ,  Edvard Kalvesten ,  Tomas Bauer

发明人： Thorbjorn Ebefors ,  Edvard Kalvesten ,  Tomas Bauer

IPC分类号： H01R9/00 ,  H01L21/302

CPC分类号： H01L21/762 ,  B81C1/00246 ,  H01L21/823481 ,  H01L23/055 ,  H01L23/147 ,  H01L23/26 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6688 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method of micro-packaging a component wherein at least a first and a second semi-conductor substrate are provided, one of which has electrical through connections (vias). A depression in either one of the substrates or in both is etched. A component is provided above vias and connected thereto. The substrates are joined to form a sealed package. A micro-packaged electronic or micromechanic device, including a thin-walled casing of a semi-conductor material having electrical through connections through the bottom of the casing is also disclosed. An electronic or micromechanic component is attached to the electrical through connections, and the package is hermetically sealed for maintaining a desired atmosphere, suitably vacuum inside the box.

摘要翻译： 一种微封装组件的方法，其中至少提供了第一和第二半导体衬底，其中一个具有电穿透连接（通路）。 在任一个基板中或两者中的凹陷被蚀刻。 在通孔上面提供一个组件并与之连接。 基板接合形成密封的包装。 还公开了一种微型封装的电子或微机电装置，其包括具有穿过套管底部的电穿透连接的半导体材料的薄壁外壳。 电子或微机械部件附接到电气通过连接件，并且封装被密封以保持期望的气氛，适当地在箱内真空。

公开(公告)号：US09362139B2

公开(公告)日：2016-06-07

申请号：US13130264

申请日：2009-11-19

申请人： Thorbjörn Ebefors ,  Edvard Kälvesten ,  Tomas Bauer

发明人： Thorbjörn Ebefors ,  Edvard Kälvesten ,  Tomas Bauer

IPC分类号： H01L21/768 ,  H01L21/60 ,  H01L21/50 ,  B81B7/00 ,  H01L21/683 ,  H01L23/552 ,  H01L23/58 ,  H01L23/64 ,  H01L23/66 ,  H01L23/04 ,  H01L23/48 ,  H01L21/78 ,  H01L23/10 ,  H01L23/00

CPC分类号： H01L21/50 ,  B81B7/007 ,  B81B2207/095 ,  B81C1/00301 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/585 ,  H01L23/642 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68363 ,  H01L2221/68372 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/29009 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29018 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/30051 ,  H01L2224/3012 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/83203 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/3512

摘要： A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices.

摘要翻译： 一种制造微电子和/或微机械装置的晶片级方法，其具有通过连接（通孔）的电晶片的封盖，包括以下步骤：提供具有第一和第二侧的半导体材料的第一晶片，以及 第一侧中的多个孔和/或凹部，以及在第二侧上延伸到晶片上方的阻挡结构，所述屏障包括绝缘材料（例如氧化物）和另一材料的外层的内层。 然后，将金属施加在所述孔中，以覆盖孔中的壁和孔的底部。 去除阻挡结构，并且通过晶片背面上的连接将接触提供给晶片。 粘合结构设置在晶片的所述第一侧或第二侧中的任一个上。 晶片被接合到另一个承载电子和微电子/机械部件的晶片，使得第一晶片形成覆盖第二晶片的封盖结构。 最后，将晶片单个化为单个器件。

公开(公告)号：US20090302414A1

公开(公告)日：2009-12-10

申请号：US12523786

申请日：2008-01-25

申请人： Thorbjörn Ebefors ,  Tomas Bauer

发明人： Thorbjörn Ebefors ,  Tomas Bauer

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/762 ,  B81C1/00246 ,  H01L21/823481 ,  H01L23/055 ,  H01L23/147 ,  H01L23/26 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6688 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

摘要： A starting substrate in the form of a semiconductor wafer (1) has a first side and a second side, the sides being plane-parallel with respect to each other, and has a thickness rendering it suitable for processing without significant risk of being damaged, for the fabrication of combined analogue and digital designs, the wafer including at least two partitions (A1, A2; DIGITAL, ANALOGUE) electrically insulated from each other by insulating material (2; 38; 81; L) extending entirely through the wafer. A method for making such substrates including etching trenches in a wafer, and filling trenches with insulating material is also described.

摘要翻译： 半导体晶片（1）形式的起始衬底具有第一侧和第二侧，所述侧面相对于彼此平行平行，并且具有使其适于处理的厚度，而没有显着的损坏风险， 为了制造组合的模拟和数字设计，晶片包括至少两个通过完全延伸穿过晶片的绝缘材料（2; 38; 81; L）彼此电绝缘的隔板（A1，A2; DIGITAL，ANALOGUE）。 还描述了制造这样的基板的方法，包括在晶片中的蚀刻沟槽，以及用绝缘材料填充沟槽。

公开(公告)号：US20100052107A1

公开(公告)日：2010-03-04

申请号：US12162600

申请日：2007-01-31

申请人： Tomas Bauer

发明人： Tomas Bauer

IPC分类号： H01L23/48 ,  H01L21/3205

CPC分类号： H01L23/49827 ,  H01L21/76898 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention relates to a method of providing a planar substrate with electrical through connections (vias). The method comprises providing a hole in said substrate and a treatment to render the substrate surface exhibiting a lower wettability than the walls inside the hole. The planar substrate is exposed to a molten material with low resistivity, whereby the molten material is drawn into the hole(s). It also relates to a semiconductor wafer as a starting substrate for electronic packaging applications, comprising low resistivity wafer through connections having closely spaced vias.

摘要翻译： 本发明涉及一种提供具有电穿透连接（通孔）的平面基板的方法。 所述方法包括在所述基底中提供孔，并且使得所述基底表面的表面具有比所述孔内的壁更低的润湿性的处理。 将平面基板暴露于具有低电阻率的熔融材料，由此将熔融材料拉入孔中。 它还涉及作为用于电子封装应用的起始衬底的半导体晶片，其包括具有紧密间隔的通孔的低电阻率晶圆通孔连接。

公开(公告)号：US09312217B2

公开(公告)日：2016-04-12

申请号：US12162599

申请日：2007-01-31

申请人： Edvard Kälvesten ,  Tomas Bauer ,  Thorbjörn Ebefors

发明人： Edvard Kälvesten ,  Tomas Bauer ,  Thorbjörn Ebefors

IPC分类号： H01L23/498 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/49827 ,  H01L21/76898 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections. Also there is provided a wafer substrate for making integrated electronic circuits and/or components, comprising a low resistivity silicon base (110) having a high resistivity top layer (122) suitable for semiconductor engineering, characterized by having low resistivity wafer through connections (140).

摘要翻译： 本发明涉及一种通过连接（140; 192）制造具有电晶片的用于半导体工程的起始衬底晶片的方法。 它包括提供具有前侧和后侧的具有低电阻率硅基底和前侧的高电阻率材料层的晶片（110,150）。 在晶片上，在高电阻率材料层中存在低电阻率材料岛。 这些岛与硅基材料接触。 沟槽从晶片的背面蚀刻，但并不全部穿过晶片，以提供通过连接（140; 192）限定晶片的绝缘外壳。 沟槽填充有绝缘材料。 然后研磨晶片的正面以露出绝缘材料，以通过连接产生晶片。 还提供了一种用于制造集成电子电路和/或部件的晶片基板，包括具有适用于半导体工程的高电阻率顶层（122）的低电阻率硅基底（110），其特征在于具有低电阻率晶圆连接（140 ）。

公开(公告)号：US08324103B2

公开(公告)日：2012-12-04

申请号：US12162600

申请日：2007-01-31

申请人： Tomas Bauer

发明人： Tomas Bauer

IPC分类号： H01L21/44

CPC分类号： H01L23/49827 ,  H01L21/76898 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention relates to a method of providing a planar substrate with electrical through connections (vias). The method comprises providing a hole in said substrate and a treatment to render the substrate surface exhibiting a lower wettability than the walls inside the hole. The planar substrate is exposed to a molten material with low resistivity, whereby the molten material is drawn into the hole(s). It also relates to a semiconductor wafer as a starting substrate for electronic packaging applications, comprising low resistivity wafer through connections having closely spaced vias.

摘要翻译： 本发明涉及一种提供具有电穿透连接（通孔）的平面基板的方法。 所述方法包括在所述基底中提供孔，并且使得所述基底表面的表面具有比所述孔内的壁更低的润湿性的处理。 将平面基板暴露于具有低电阻率的熔融材料，由此将熔融材料拉入孔中。 它还涉及作为用于电子封装应用的起始衬底的半导体晶片，其包括具有紧密间隔的通孔的低电阻率晶圆通孔连接。

公开(公告)号：US08598676B2

公开(公告)日：2013-12-03

申请号：US13566081

申请日：2012-08-03

申请人： Thorbjörn Ebefors ,  Tomas Bauer

发明人： Thorbjörn Ebefors ,  Tomas Bauer

IPC分类号： H01L29/06

CPC分类号： H01L21/762 ,  B81C1/00246 ,  H01L21/823481 ,  H01L23/055 ,  H01L23/147 ,  H01L23/26 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6688 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

摘要： A starting substrate in the form of a semiconductor wafer (1) has a first side and a second side, the sides being plane-parallel with respect to each other, and has a thickness rendering it suitable for processing without significant risk of being damaged, for the fabrication of combined analogue and digital designs, the wafer including at least two partitions (A1, A2; DIGITAL, ANALOGUE) electrically insulated from each other by insulating material (2; 38; 81; L) extending entirely through the wafer. A method for making such substrates including etching trenches in a wafer, and filling trenches with insulating material is also described.

摘要翻译： 半导体晶片（1）形式的起始衬底具有第一侧和第二侧，所述侧面相对于彼此平行平行，并且具有使其适于处理的厚度，而没有显着的损坏风险， 为了制造组合的模拟和数字设计，晶片包括至少两个通过完全延伸穿过晶片的绝缘材料（2; 38; 81; L）彼此电绝缘的隔板（A1，A2; DIGITAL，ANALOGUE）。 还描述了制造这样的基板的方法，包括在晶片中的蚀刻沟槽，以及用绝缘材料填充沟槽。

公开(公告)号：US20120292736A1

公开(公告)日：2012-11-22

申请号：US13566081

申请日：2012-08-03

申请人： Thorbjörn Ebefors ,  Tomas Bauer

发明人： Thorbjörn Ebefors ,  Tomas Bauer

IPC分类号： H01L29/06

CPC分类号： H01L21/762 ,  B81C1/00246 ,  H01L21/823481 ,  H01L23/055 ,  H01L23/147 ,  H01L23/26 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6688 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

摘要： A starting substrate in the form of a semiconductor wafer (1) has a first side and a second side, the sides being plane-parallel with respect to each other, and has a thickness rendering it suitable for processing without significant risk of being damaged, for the fabrication of combined analogue and digital designs, the wafer including at least two partitions (A1, A2; DIGITAL, ANALOGUE) electrically insulated from each other by insulating material (2; 38; 81; L) extending entirely through the wafer. A method for making such substrates including etching trenches in a wafer, and filling trenches with insulating material is also described.

摘要翻译： 半导体晶片（1）形式的起始衬底具有第一侧和第二侧，所述侧面相对于彼此平行平行，并且具有使其适于处理的厚度，而没有显着的损坏风险， 为了制造组合的模拟和数字设计，晶片包括至少两个通过完全延伸穿过晶片的绝缘材料（2; 38; 81; L）彼此电绝缘的隔板（A1，A2; DIGITAL，ANALOGUE）。 还描述了制造这样的基板的方法，包括在晶片中的蚀刻沟槽，以及用绝缘材料填充沟槽。

公开(公告)号：US20120267773A1

公开(公告)日：2012-10-25

申请号：US13130264

申请日：2009-11-19

申请人： Thorbjörn Ebefors ,  Edvard Kälvesten ,  Tomas Bauer

发明人： Thorbjörn Ebefors ,  Edvard Kälvesten ,  Tomas Bauer

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/04 ,  H01L21/60

CPC分类号： H01L21/50 ,  B81B7/007 ,  B81B2207/095 ,  B81C1/00301 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/585 ,  H01L23/642 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68363 ,  H01L2221/68372 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/29009 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29018 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/30051 ,  H01L2224/3012 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/83203 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/3512

摘要： A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices.

摘要翻译： 一种制造微电子和/或微机械装置的晶片级方法，其具有通过连接（通孔）的电晶片的封盖，包括以下步骤：提供具有第一和第二侧的半导体材料的第一晶片，以及 第一侧中的多个孔和/或凹部，以及在第二侧上延伸到晶片上方的阻挡结构，所述屏障包括绝缘材料（例如氧化物）和另一材料的外层的内层。 然后，将金属施加在所述孔中，以覆盖孔中的壁和孔的底部。 去除阻挡结构，并且通过晶片背面上的连接将接触提供给晶片。 粘合结构设置在晶片的所述第一侧或第二侧中的任一个上。 晶片被接合到另一个承载电子和微电子/机械部件的晶片，使得第一晶片形成覆盖第二晶片的封盖结构。 最后，将晶片单个化为单个器件。