专利检索 ap:("Ting Zhong" OR "Valery Dubin" OR "Ming Fang") AND inv:"Ming Fang" 第 1 页

1.

发明申请
Forming a barrier layer in interconnect joints and structures formed thereby 有权
标题翻译：在互连接头和由此形成的结构中形成阻挡层

公开(公告)号：US20060205234A1

公开(公告)日：2006-09-14

申请号：US11078611

申请日：2005-03-11

申请人： Ting Zhong , Valery Dubin , Ming Fang

发明人： Ting Zhong , Valery Dubin , Ming Fang

IPC分类号： H01L21/31 , H01L21/469

CPC分类号： H01L21/2885 , H01L21/7685 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/05655 , H01L2224/13099 , H01L2924/00014 , H01L2924/01011 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/15747 , H01L2924/00 , H01L2224/05099

摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a barrier layer on a substrate, wherein the barrier layer comprises molybdenum; and forming a lead free interconnect structure on the barrier layer.

摘要翻译： 描述形成微电子结构的方法。这些方法的实施例包括在衬底上形成阻挡层，其中阻挡层包含钼; 以及在阻挡层上形成无铅互连结构。

2.

发明申请
FORMING A BARRIER LAYER IN JOINT STRUCTURES 审中-公开
标题翻译：在联合结构中形成障碍层

公开(公告)号：US20070123025A1

公开(公告)日：2007-05-31

申请号：US11627812

申请日：2007-01-26

申请人： Ting Zhong , Valery Dubin , Ming Fang

发明人： Ting Zhong , Valery Dubin , Ming Fang

IPC分类号： H01L21/4763 , H01L23/48

CPC分类号： H01L21/2885 , H01L21/7685 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/05655 , H01L2224/13099 , H01L2924/00014 , H01L2924/01011 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/15747 , H01L2924/00 , H01L2224/05099

摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a barrier layer on a substrate, wherein the barrier layer comprises molybdenum; and forming a lead free interconnect structure on the barrier layer.

摘要翻译： 描述形成微电子结构的方法。这些方法的实施例包括在衬底上形成阻挡层，其中阻挡层包含钼; 以及在阻挡层上形成无铅互连结构。

3.

发明授权
Forming a barrier layer in interconnect joints and structures formed thereby 有权
标题翻译：在互连接头和由此形成的结构中形成阻挡层

公开(公告)号：US07416980B2

公开(公告)日：2008-08-26

申请号：US11078611

申请日：2005-03-11

申请人： Ting Zhong , Valery Dubin , Ming Fang

发明人： Ting Zhong , Valery Dubin , Ming Fang

IPC分类号： H01L21/44

CPC分类号： H01L21/2885 , H01L21/7685 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/05655 , H01L2224/13099 , H01L2924/00014 , H01L2924/01011 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/15747 , H01L2924/00 , H01L2224/05099

摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a barrier layer on a substrate, wherein the barrier layer comprises molybdenum; and forming a lead free interconnect structure on the barrier layer.

摘要翻译： 描述形成微电子结构的方法。这些方法的实施例包括在衬底上形成阻挡层，其中阻挡层包含钼; 以及在阻挡层上形成无铅互连结构。

4.

发明授权
Large bumps for optical flip chips 有权

公开(公告)号：US06933171B2

公开(公告)日：2005-08-23

申请号：US10691136

申请日：2003-10-21

申请人： Ming Fang , Valery Dubin , Daoqiang Lu

发明人： Ming Fang , Valery Dubin , Daoqiang Lu

IPC分类号： G02B6/42 , H01L21/00 , H01L21/44 , H01L21/48 , H01L21/50 , H01L21/60 , H01L23/48 , H01L23/485 , H01L23/52 , H01L27/15 , H01L29/267 , H01L31/12 , H01L33/00

CPC分类号： H01L24/16 , G02B6/4204 , G02B6/4232 , H01L24/11 , H01L24/81 , H01L2224/1134 , H01L2224/1147 , H01L2224/13099 , H01L2224/13144 , H01L2224/16 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/15151 , H01L2924/19041 , H01L2924/19043 , H01L2924/00014 , H01L2924/00015 , H01L2224/29099

摘要： The invention provides bumps between a die and a substrate with a height greater than or equal to a height of a waveguide between the die and the substrate. The bumps may be formed on a die prior to that die being singulated from a wafer.

5.

发明申请
Method for constructing contact formations 有权
标题翻译：构造接触层的方法

公开(公告)号：US20060134902A1

公开(公告)日：2006-06-22

申请号：US11019857

申请日：2004-12-21

申请人： Valery Dubin , Tzuen-Luh Huang , Ming Fang , Kevin Lee , Yuehai Liang , Margherita Chang

发明人： Valery Dubin , Tzuen-Luh Huang , Ming Fang , Kevin Lee , Yuehai Liang , Margherita Chang

IPC分类号： H01L21/44

CPC分类号： H01L21/2885 , C25D3/02 , C25D3/38 , C25D5/10 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05572 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1147 , H01L2224/13099 , H01L2924/01005 , H01L2924/01011 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , H01L2924/00014 , H01L2924/0496

摘要： According to one aspect of the invention, a method for forming contact formations is provided. A substrate may be placed in an electrolytic solution. The substrate may have an exposed conductive portion and the electrolytic solution may include a plurality of metallic ions and an accelerator. The accelerator may include at least one of bis-(sodium sulfopropyl)-disulfide and 3-mercapto-1-propanesulfonic acid-sodium salt. A voltage may be applied across the electrolytic solution and the conductive portion of the substrate to cause the metallic ions to be changed into metallic particles and deposited on the conductive portion. The electrolytic solution may also include a protonated organic additive. The electrolytic solution may also include an acid and a surfactant. The acid may include at least one of sulfuric acid, methane sulfonic acid, benzene sulfonic acid, and picryl sulfonic acid. The surfactant may include at least one of polyethylene glycol and polypropylene glycol.

摘要翻译： 根据本发明的一个方面，提供了形成接触层的方法。衬底可以放置在电解溶液中。基板可以具有暴露的导电部分，电解液可以包括多个金属离子和加速器。促进剂可以包括双 - （磺基磺基丙基） - 二硫化物和3-巯基-1-丙磺酸钠盐中的至少一种。可以在电解液和基板的导电部分之间施加电压，以使金属离子变成金属颗粒并沉积在导电部分上。电解液还可以包括质子化的有机添加剂。电解液还可以包含酸和表面活性剂。酸可以包括硫酸，甲磺酸，苯磺酸和苦基磺酸中的至少一种。表面活性剂可以包括聚乙二醇和聚丙二醇中的至少一种。

6.

发明授权
Method and apparatus for filling interlayer vias on ferroelectric polymer substrates 失效
标题翻译：在铁电聚合物基板上填充层间通孔的方法和装置

公开(公告)号：US07001782B1

公开(公告)日：2006-02-21

申请号：US10747824

申请日：2003-12-29

申请人： Daniel C. Diana , Ebrahim Andideh , Richard M. Steger , Valery Dubin , Ming Fang

发明人： Daniel C. Diana , Ebrahim Andideh , Richard M. Steger , Valery Dubin , Ming Fang

IPC分类号： H01L21/00

CPC分类号： H01L21/76802 , H01L21/288 , H01L21/76877

摘要： Some embodiments for a method to fill interlayer vias with a suitable metal in a ferroelectric polymer memory die to reduce the step height and improve the thermal and electrical properties of the via. The method uses an electroless plating method to fill the vias, which is compatible with the ferroelectric polymer memory die processing temperature limits. The resulting process produces via fill metal plugs in the ferroelectric memory die, which allows for the deposition of a thin metal layer over the vias, while at the same time improving the electrical and thermal properties of the vias. Other embodiments are described and claimed herein.

摘要翻译： 用于在铁电聚合物存储器管芯中用合适的金属填充层间通孔的方法的一些实施例，以降低台阶高度并改善通孔的热和电特性。该方法采用化学镀方法填充通孔，这与铁电聚合物记忆芯片加工温度的极限相兼容。所得到的工艺通过铁电存储器管芯中的填充金属塞产生，其允许在通孔上沉积薄金属层，同时改善通孔的电气和热性能。在此描述和要求保护的其它实施例。