Method and apparatus for filling interlayer vias on ferroelectric polymer substrates
    5.
    发明授权
    Method and apparatus for filling interlayer vias on ferroelectric polymer substrates 失效
    在铁电聚合物基板上填充层间通孔的方法和装置

    公开(公告)号:US07001782B1

    公开(公告)日:2006-02-21

    申请号:US10747824

    申请日:2003-12-29

    IPC分类号: H01L21/00

    摘要: Some embodiments for a method to fill interlayer vias with a suitable metal in a ferroelectric polymer memory die to reduce the step height and improve the thermal and electrical properties of the via. The method uses an electroless plating method to fill the vias, which is compatible with the ferroelectric polymer memory die processing temperature limits. The resulting process produces via fill metal plugs in the ferroelectric memory die, which allows for the deposition of a thin metal layer over the vias, while at the same time improving the electrical and thermal properties of the vias. Other embodiments are described and claimed herein.

    摘要翻译: 用于在铁电聚合物存储器管芯中用合适的金属填充层间通孔的方法的一些实施例,以降低台阶高度并改善通孔的热和电特性。 该方法采用化学镀方法填充通孔,这与铁电聚合物记忆芯片加工温度的极限相兼容。 所得到的工艺通过铁电存储器管芯中的填充金属塞产生,其允许在通孔上沉积薄金属层,同时改善通孔的电气和热性能。 在此描述和要求保护的其它实施例。