公开(公告)号：US20180143536A1

公开(公告)日：2018-05-24

申请号：US15817724

申请日：2017-11-20

Applicant: Tokyo Electron Limited ,  Tokyo Ohka Kogyo Co., Ltd.

Inventor： Hidetami YAEGASHI ,  Kenichi OYAMA ,  Katsumi OHMORI ,  Yoshitaka KOMURO ,  Takehiro SESHIMO

IPC: G03F7/20 ,  G06F17/50 ,  H01L21/3213 ,  H01L21/033 ,  G03F1/76 ,  G03F1/36

CPC classification number: G03F7/202 ,  G03F1/36 ,  G03F1/76 ,  G06F17/5081 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/768 ,  H01L23/544 ,  H01L2223/54426

Abstract: A pattern forming method includes forming a first film patterned in a line and space shape on an underlayer film, the line and space shape including lines and a space arranged therebetween, forming a second film to cover the first film, removing the second film to form the second film on a side surface of the first film in a line shape, forming a third film to cover the first film and the second film, removing the third film formed on the first film and the second film to form the third film on a side surface of the second film, and converting the third film after removing the third film formed on the first film and the second film, wherein the third film is comprised of an organic metal compound, the organic metal compound having characteristic to increase etching tolerance when the organic metal compound undergoes a predetermined process.

公开(公告)号：US20160358769A1

公开(公告)日：2016-12-08

申请号：US15237840

申请日：2016-08-16

Applicant: TOKYO ELECTRON LIMITED

Inventor： Hidetami YAEGASHI ,  Kenichi OYAMA ,  Masatoshi YAMATO ,  Tomohiro ISEKI ,  Toyohisa TSURUDA

IPC: H01L21/027 ,  G03F7/36 ,  G03F7/004 ,  G03F7/20

CPC classification number: H01L21/0273 ,  G03F7/0045 ,  G03F7/20 ,  G03F7/36 ,  H01L21/0276

Abstract: There is provided a semiconductor device manufacturing method, including: a film forming process in which, by supplying a solution for modifying a surface layer of a resist to a target object having a resist pattern and allowing the solution to infiltrate into the resist, a film having elasticity and having no compatibility with the resist is formed in the surface layer of the resist; and a heating process in which the target object having the film formed thereon is heated.

Abstract translation: 提供了一种半导体器件制造方法，包括：成膜工艺，其中通过向具有抗蚀图案的目标物体提供用于将抗蚀剂的表面层修饰的溶液并且使溶液渗入抗蚀剂中的膜， 在抗蚀剂的表面层中形成具有弹性且与抗蚀剂不相容的物质; 以及加热其中形成有膜的目标物体的加热过程。

公开(公告)号：US20160049292A1

公开(公告)日：2016-02-18

申请号：US14818409

申请日：2015-08-05

Applicant: TOKYO ELECTRON LIMITED

Inventor： Hidetami YAEGASHI ,  Kenichi OYAMA ,  Masatoshi YAMATO ,  Tomohiro ISEKI ,  Toyohisa TSURUDA

IPC: H01L21/027 ,  H01L21/02

CPC classification number: H01L21/0273 ,  G03F7/0045 ,  G03F7/20 ,  G03F7/36 ,  H01L21/0276

Abstract: There is provided a semiconductor device manufacturing method, including: a film forming process in which, by supplying a solution for modifying a surface layer of a resist to a target object having a resist pattern and allowing the solution to infiltrate into the resist, a film having elasticity and having no compatibility with the resist is formed in the surface layer of the resist; and a heating process in which the target object having the film formed thereon is heated.

Abstract translation: 提供了一种半导体器件制造方法，包括：成膜工艺，其中通过向具有抗蚀图案的目标物体提供用于将抗蚀剂的表面层修饰的溶液并且使溶液渗入抗蚀剂中的膜， 在抗蚀剂的表面层中形成具有弹性且与抗蚀剂不相容的物质; 以及加热其中形成有膜的目标物体的加热过程。

公开(公告)号：US20140083972A1

公开(公告)日：2014-03-27

申请号：US14036748

申请日：2013-09-25

Applicant: Tokyo Electron Limited

Inventor： Kenichi OYAMA ,  Hidetami YAEGASHI

IPC: H01B13/00

CPC classification number: H01B13/003 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: Provided is a pattern forming method which includes forming fine lines and spaces in a thin film on a substrate; forming a first pattern which is a reverse pattern of a trench pattern for forming wiring by cutting the lines; and forming a second pattern which will become the trench pattern by reversing the first pattern.

Abstract translation: 提供一种图案形成方法，其包括在基板上形成薄膜中的细线和空间; 形成作为用于通过切割线形成布线的沟槽图案的反向图案的第一图案; 并且通过反转第一图案形成将成为沟槽图案的第二图案。

公开(公告)号：US20220406572A1

公开(公告)日：2022-12-22

申请号：US17755406

申请日：2020-10-15

Applicant: Tokyo Electron Limited

Inventor： Kenichi OYAMA ,  Shohei YAMAUCHI ,  Kazuya DOBASHI ,  Akitaka SHIMIZU

IPC: H01J37/32 ,  H01L21/3065 ,  H01L21/02

Abstract: The present disclosure appropriately shortens a processing step for processing a substrate in which a silicon layer and a silicon germanium layer are alternatively laminated. The present disclosure provides a substrate processing method of processing the substrate in which the silicon layer and the silicon germanium layer are alternatively laminated, which includes forming an oxide film by selectively modifying a surface layer of an exposed surface of the silicon germanium layer by using a processing gas including fluorine and oxygen and converted into plasma.

公开(公告)号：US20250092514A1

公开(公告)日：2025-03-20

申请号：US18970324

申请日：2024-12-05

Applicant: Tokyo Electron Limited

Inventor： Masanobu IGETA ,  Yutaka TAKAHASHI ,  Tatsuya TAMURA ,  Yusuke SUZUKI ,  Toyohiro KAMADA ,  Kenichi OYAMA ,  Reiko TSUZUKI ,  Seiji NAGAHARA ,  Makoto MURAMATSU ,  Satoru MURAMATSU ,  Satoru SHIMURA

IPC: C23C16/40 ,  C23C16/56 ,  G03F7/20 ,  G03F7/40

Abstract: A substrate processing method includes forming a metal oxide resist film on a substrate including an underlayer; forming a pattern in the metal oxide resist film; modifying the metal oxide resist film in which the pattern has been formed; and etching the underlayer by using the modified metal oxide resist film as a mask.

公开(公告)号：US20140235065A1

公开(公告)日：2014-08-21

申请号：US14182678

申请日：2014-02-18

Applicant: TOKYO ELECTRON LIMITED

Inventor： Hidetami YAEGASHI ,  Kenichi OYAMA ,  Masatoshi YAMATO

IPC: H01L21/02

CPC classification number: H01L21/0273 ,  H01L21/6715

Abstract: Disclosed is a semiconductor device manufacturing method that manufactures a semiconductor device having a resist pattern which is excellent in roughness property and line width property. The method includes forming a film which is elastic and incompatible with a resist patterned on an object to be processed to cover the surface of the resist, and heating the object to be processed formed with the film.

Abstract translation: 公开了一种半导体器件制造方法，其制造具有优异的粗糙度和线宽特性的抗蚀剂图案的半导体器件。 该方法包括形成与被处理物体上图案化的抗蚀剂弹性地不相容的膜，以覆盖抗蚀剂的表面，并加热形成有被膜的被处理物体。

公开(公告)号：US20140162428A1

公开(公告)日：2014-06-12

申请号：US14177858

申请日：2014-02-11

Applicant: TOKYO ELECTRON LIMITED

Inventor： Hajime NAKABAYASHI ,  Kenichi OYAMA ,  Yoshihiro HIROTA

IPC: H01L45/00

CPC classification number: H01L45/1683 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/1675

Abstract: A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole.

Abstract translation: 相变存储器包括在基板上的绝缘层，具有一极的电极层和在绝缘层内具有另一极的电极层，其绝缘层的上部的下部基本上为正方形或大致矩形的开口部 ，形成为沿基板的表面大致平行于开口部的下部的各侧的相变部，以及具有极点的两个连接电极，并在该下部的两个相对的拐角处与相变部连接 连接到具有一个极的电极层的二极管部分和相变部分的开口部分，以及具有另一个极点的两个连接电极，并且在连接相变部分和电极层的另外两个相对的拐角处连接到相变部分 有另一个极点。

公开(公告)号：US20140094034A1

公开(公告)日：2014-04-03

申请号：US14038345

申请日：2013-09-26

Applicant: Tokyo Electron Limited

Inventor： Kenichi OYAMA ,  Hidetami YAEGASHI

IPC: H01L21/306

CPC classification number: H01L21/306 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/3086

Abstract: A pattern forming method includes forming a pattern forming material film on a substrate as an etching target film, the pattern forming material film having an exposing section that has porosity upon exposure and a non-exposing section, patterning and exposing the pattern forming material film for the exposing section to have the porosity, selectively infiltrating a filling material into voids of the exposing section to reinforce the exposing section, and removing the non-exposing section of the pattern forming material film by dry etching to form a predetermined pattern.

Abstract translation: 图案形成方法包括在基板上形成图案形成材料膜作为蚀刻靶膜，所述图案形成材料膜具有曝光时具有孔隙率的曝光部分和非曝光部分，图案化和曝光图案形成材料膜，用于 暴露部分具有孔隙率，选择性地将填充材料渗透到曝光部分的空隙中以加强曝光部分，以及通过干蚀刻去除图案形成材料膜的非曝光部分以形成预定图案。