公开(公告)号：US06889430B2

公开(公告)日：2005-05-10

申请号：US10020352

申请日：2001-12-12

Applicant: Tongbi Jiang ,  Partrick Tandy

Inventor： Tongbi Jiang ,  Partrick Tandy

IPC: H01L23/31 ,  H01L23/495 ,  H05K3/34

CPC classification number: H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49171 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of selectively adjusting surface tension of a soldermask material. Specifically, a method of selectively adjusting the surface tension of a soldermask material to promote adhesion of a molding compound in a ball grid array package while maintaining a low surface tension on the ball attach area to prevent bridging between the solder balls. Solder balls require a low surface tension soldermask to minimize bridging, while the molding compound requires a high surface tension to provide adequate adhesion to the surface of the soldermask. By exposing selected portions of the soldermask to an activation method, such as ultra-violet radiation, the surface tension of the soldermask can be varied such that different areas of the package exhibit different surface tensions.

Abstract translation: 选择性地调节焊接材料的表面张力的方法。 具体地说，可以选择性地调节焊料材料的表面张力以促进模塑料在球栅阵列封装中的粘附，同时保持球附着区域上的低表面张力以防止焊球之间的桥接。 焊球需要低表面张力焊接掩模以最小化桥接，而模塑料需要高表面张力以提供对焊接表面的足够的粘附。 通过将焊接掩模的选定部分暴露于诸如紫外辐射的激活方法，可以改变焊接掩模的表面张力，使得封装的不同区域表现出不同的表面张力。

公开(公告)号：US06388199B1

公开(公告)日：2002-05-14

申请号：US09628833

申请日：2000-07-31

Applicant: Tongbi Jiang ,  Partrick Tandy

Inventor： Tongbi Jiang ,  Partrick Tandy

IPC: H05K103

CPC classification number: H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49171 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of selectively adjusting surface tension of a soldermask material. Specifically, a method of selectively adjusting the surface tension of a soldermask material to promote adhesion of a molding compound in a ball grid array package while maintaining a low surface tension on the ball attach area to prevent bridging between the solder balls. Solder balls require a low surface tension soldermask to minimize bridging, while the molding compound requires a high surface tension to provide adequate adhesion to the surface of the soldermask. By exposing selected portions of the soldermask to an activation method, such as ultra-violet radiation, the surface tension of the soldermask can be varied such that different areas of the package exhibit different surface tensions.

Abstract translation: 选择性地调节焊接材料的表面张力的方法。 具体地说，可以选择性地调节焊料材料的表面张力以促进模塑料在球栅阵列封装中的粘附，同时保持球附着区域上的低表面张力以防止焊球之间的桥接。 焊球需要低表面张力焊接掩模以最小化桥接，而模塑料需要高表面张力以提供对焊接表面的足够的粘附。 通过将焊接掩模的选定部分暴露于诸如紫外辐射的激活方法，可以改变焊接掩模的表面张力，使得封装的不同区域表现出不同的表面张力。

公开(公告)号：US08922002B2

公开(公告)日：2014-12-30

申请号：US12796011

申请日：2010-06-08

Applicant: Young Do Kweon ,  Tongbi Jiang

Inventor： Young Do Kweon ,  Tongbi Jiang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L23/544 ,  H01L21/48

CPC classification number: H01L24/742 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/566 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/11 ,  H01L24/12 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54486 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/11013 ,  H01L2224/11015 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/7598 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/384 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

Abstract translation: 本文公开了在半导体工件上形成多个微电子器件的微电子器件和方法。 一种这样的方法包括将多个第一互连元件放置在半导体工件的一侧上，在工件侧面上形成层，通过加热第一互连元件来重塑第一互连元件，以及将多个第一互连元件的第一部分 单独的第二互连元件到相应的第一互连元件，其中所述单个第二互连元件的第二部分被暴露。

公开(公告)号：US08723307B2

公开(公告)日：2014-05-13

申请号：US12852925

申请日：2010-08-09

Applicant: Tongbi Jiang ,  Yong Poo Chia

Inventor： Tongbi Jiang ,  Yong Poo Chia

IPC: H01L23/04

CPC classification number: H01L25/071 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76877 ,  H01L21/82 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/83193 ,  H01L2224/838 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

Abstract: A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.

Abstract translation: 公开了一种装置，其包括至少一个集成电路管芯，其至少一部分位于密封材料的主体中，以及延伸穿过密封材料本体的至少一个导电通孔。

公开(公告)号：US20110233745A1

公开(公告)日：2011-09-29

申请号：US13154540

申请日：2011-06-07

Applicant: Setho Sing Fee ,  Lim Thiam Chye ,  Tongbi Jiang

Inventor： Setho Sing Fee ,  Lim Thiam Chye ,  Tongbi Jiang

IPC: H01L23/495

CPC classification number: H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.

Abstract translation: 一些实施例包括组装集成电路封装的方法，其中在半导体管芯的接合焊盘区域上形成至少两个不同的导电层，并且其中与插入件相关联的导电突起通过金球结合到 至少两个导电层。 导电层可以包括银，金，铜，铬，镍，钯，铂，钽，钛，钒和钨中的一种或多种。 在一些实施例中，接合焊盘区域可以包括铝，导电层的内部可以包括镍，导电层的外部可以包括金，与中介层相关联的导电突起可以包括金; 并且热超声键合可以包括插入物突起与金球的金 - 金结合，以及外导体层与金球的金 - 金结合。 一些实施例包括集成电路封装。

公开(公告)号：US07749882B2

公开(公告)日：2010-07-06

申请号：US11509441

申请日：2006-08-23

Applicant: Young Do Kweon ,  Tongbi Jiang

Inventor： Young Do Kweon ,  Tongbi Jiang

IPC: H01L21/44

CPC classification number: H01L24/742 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/566 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/11 ,  H01L24/12 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54486 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/11013 ,  H01L2224/11015 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/7598 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/384 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

Abstract translation: 本文公开了在半导体工件上形成多个微电子器件的微电子器件和方法。 一种这样的方法包括将多个第一互连元件放置在半导体工件的一侧上，在工件侧面上形成层，通过加热第一互连元件来重塑第一互连元件，以及将多个第一互连元件的第一部分 单独的第二互连元件到相应的第一互连元件，其中所述单个第二互连元件的第二部分被暴露。

公开(公告)号：US07700406B2

公开(公告)日：2010-04-20

申请号：US11770451

申请日：2007-06-28

Applicant: Setho Sing Fee ,  Lim Thiam Chye ,  Tongbi Jiang

Inventor： Setho Sing Fee ,  Lim Thiam Chye ,  Tongbi Jiang

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/66 ,  H01L21/44

CPC classification number: H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.

Abstract translation: 一些实施例包括组装集成电路封装的方法，其中在半导体管芯的接合焊盘区域上形成至少两个不同的导电层，并且其中与插入件相关联的导电突起通过金球结合到 至少两个导电层。 导电层可以包括银，金，铜，铬，镍，钯，铂，钽，钛，钒和钨中的一种或多种。 在一些实施例中，接合焊盘区域可以包括铝，导电层的内部可以包括镍，导电层的外部可以包括金，与中介层相关联的导电突起可以包括金; 并且热超声键合可以包括插入物突起与金球的金 - 金结合，以及外导体层与金球的金 - 金结合。 一些实施例包括集成电路封装。

公开(公告)号：US20090146234A1

公开(公告)日：2009-06-11

申请号：US11951528

申请日：2007-12-06

Applicant: Shijian Luo ,  Tongbi Jiang ,  J. Michael Brooks

Inventor： Shijian Luo ,  Tongbi Jiang ,  J. Michael Brooks

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L27/14618 ,  H01L27/14634 ,  H01L27/14683 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Infrared (IR) absorbing layers and microelectronic imaging units that employ such layers are disclosed herein. In one embodiment, a method of manufacturing a microelectronic imaging unit includes attaching an IR-absorbing lamina having a filler material to a backside die surface of an imager workpiece. An individual imaging die is singulated from the workpiece such that a section of the infrared-absorbing lamina remains attached to the individual imaging die. The individual imaging die is coupled to an interposer substrate with a portion of the IR-absorbing lamina positioned therebetween. In another embodiment, the IR-absorbing lamina is a die attach film and the filler material is carbon black.

Abstract translation: 本文公开了采用这种层的红外（IR）吸收层和微电子成像单元。 在一个实施例中，制造微电子成像单元的方法包括将具有填充材料的IR吸收层附着到成像器工件的背面模具表面上。 单个成像管芯从工件分离，使得红外线吸收层的一部分保持附着到各个成像管芯。 单个成像管芯耦合到插入器衬底，其中IR吸收层的一部分位于它们之间。 在另一个实施方案中，IR吸收层是芯片附着膜，填充材料是炭黑。

公开(公告)号：US20090102002A1

公开(公告)日：2009-04-23

申请号：US11969613

申请日：2008-01-04

Applicant: Yong Poo Chia ,  Tongbi Jiang

Inventor： Yong Poo Chia ,  Tongbi Jiang

IPC: H01L31/00 ,  H01L21/60

CPC classification number: H01L27/14618 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L27/14683 ,  H01L2224/04105 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: Semiconductor packages, packaged semiconductor devices, methods of manufacturing semiconductor packages, methods of packaging semiconductor devices, and associated systems are disclosed. A semiconductor package in accordance with a particular embodiment includes a die having a first side carrying a first bond site electrically connected to a sensor and/or a transmitter configured to receive and/or transmit radiation signals. The semiconductor package also includes encapsulant material at least partially encapsulating a portion of the die. The semiconductor package includes a conductive path from the first bond site to a second bond site, positioned on a back surface of the encapsulant, which can include through-encapsulant interconnects. A cover can be positioned adjacent to the die and be generally transparent to a target wavelength.

Abstract translation: 公开了半导体封装，封装半导体器件，制造半导体封装的方法，封装半导体器件的方法以及相关系统。 根据特定实施例的半导体封装包括具有第一侧的管芯，其具有电连接到传感器的第一接合位置和/或被配置为接收和/或发送辐射信号的发射器。 半导体封装还包括至少部分地封装模具的一部分的密封剂材料。 半导体封装包括从第一结合位点到第二结合位置的导电路径，其位于密封剂的后表面上，其可以包括通过封装的互连。 盖可以邻近管芯定位，并且对于目标波长通常是透明的。

公开(公告)号：US07476277B2

公开(公告)日：2009-01-13

申请号：US10701140

申请日：2003-11-04

Applicant: Tongbi Jiang ,  Chad A. Cobbley ,  John VanNortwick

Inventor： Tongbi Jiang ,  Chad A. Cobbley ,  John VanNortwick

IPC: B05C11/00

CPC classification number: B41C1/14 ,  B41N1/242 ,  H01L2224/4826 ,  H05K3/1225 ,  Y10S438/945

Abstract: A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.

Abstract translation: 公开了一种用于改进模板/丝网印刷质量的方法和装置。 在片上（LOC）包装过程中，模板或屏幕有助于将可印刷材料施加到基底上，例如对半导体晶片的半导体管芯的粘合剂。 在一个实施例中，模板包括施加到模板或筛网的图案的至少一个表面上的涂层，以阻止可印刷材料运动到表面上。 在另一个实施例中，模板或丝网包括施加到图案的至少一个其他表面的第二涂层，以促进可印刷材料在基底上的铺展。