公开(公告)号：US06560863B2

公开(公告)日：2003-05-13

申请号：US09924807

申请日：2001-08-08

申请人： Toshinori Koyama ,  Mikiko Kobayashi ,  Atsuhiko Hattori

发明人： Toshinori Koyama ,  Mikiko Kobayashi ,  Atsuhiko Hattori

IPC分类号： H05K310

CPC分类号： H05K3/4661 ,  H05K3/381 ,  H05K3/4602 ,  H05K2203/095 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A method of producing a wiring board having a plurality of wiring layers each being located on an electrical insulation layer, in which an electrical insulation layer is formed on a substrate using a resin material, and a conductor layer is formed on the surface of the electrical insulation layer by successive electroless plating and electroplating with copper, and is patterned to form a wiring layer, wherein, after the formation of the electrical insulation layer on the substrate, the electrical insulation layer is subjected to a plasma treatment and a subsequent ultraviolet treatment, and the electroless plating and the electroplating are then performed.

公开(公告)号：US20050094120A1

公开(公告)日：2005-05-05

申请号：US10974327

申请日：2004-10-27

申请人： Kazunari Sekigawa ,  Toshinori Koyama ,  Kazutaka Kobayashi ,  Masatoshi Akagawa

发明人： Kazunari Sekigawa ,  Toshinori Koyama ,  Kazutaka Kobayashi ,  Masatoshi Akagawa

IPC分类号： G03F7/20 ,  G03B27/54 ,  H01L21/027 ,  H05K3/00

CPC分类号： G03F7/70283 ,  G03F7/70291 ,  H05K3/0002 ,  H05K3/0005 ,  H05K3/0082

摘要： A direct exposure system comprises: a data mask that is a data object including drawing data; and a control mask that is a data object including at least one logical layer in which information about exposure conditions applied according to regions on a substrate is specified, and performs a direct exposure process using integrated data generated by combining the data mask with the control mask.

摘要翻译： 直接曝光系统包括：作为包括绘图数据的数据对象的数据掩模; 以及作为包括至少一个逻辑层的控制掩模，所述至少一个逻辑层指定了根据基板上的区域应用的关于曝光条件的信息，并且使用通过将数据掩模与控制掩模组合而生成的积分数据进行直接曝光处理 。

公开(公告)号：US06254758B1

公开(公告)日：2001-07-03

申请号：US09243507

申请日：1999-02-01

申请人： Toshinori Koyama

发明人： Toshinori Koyama

IPC分类号： C23C2802

CPC分类号： C23F1/18 ,  H05K3/067 ,  H05K3/108 ,  H05K3/181 ,  H05K2203/0796 ,  H05K2203/121

摘要： A method of forming a conductor pattern on a wiring board, in which a conductor pattern forming process on the wiring board can be simplified; and an interval between the conductor patterns can be further reduced by suppressing the etching conducted on the side portions of the electrolytic copper plated layer. The method of forming a conductor pattern on a wiring board in which an electroless copper plated layer 12 is formed on a surface of an insulating layer 10 of the wiring board and an electrolytic copper plated layer 16 is formed on the electroless copper plated layer 12, comprises the steps of: forming an electroless copper plated layer 12 on the insulating layer 10; forming and patterning a layer of resist 14 on the electroless copper plated layer 12; forming an electrolytic copper plated layer 16 on the electroless copper plated layer 12 exposed from the layer of plated resist 14; removing the layer of plated resist 14 for exposing the electroless copper plated layer 12 except for a portion in which the electrolytic copper plated layer 16 is formed; and removing the exposed electroless copper plated layer 12 by using an etching solution composed of a mixed aqueous solution containing sulfuric acid, hydrogen peroxide and Cu chelate agent.

摘要翻译： 在布线基板上形成导体图案的方法，其中可以简化布线板上的导体图形形成处理; 并且通过抑制在电解镀铜层的侧面进行的蚀刻，可以进一步减小导体图案之间的间隔。 在化学镀铜层12上形成在布线基板的绝缘层10的表面上形成化学镀铜层12的布线基板上形成导体图案的方法和电解镀铜层16， 包括以下步骤：在绝缘层10上形成化学镀铜层12; 在化学镀铜层12上形成和图案化抗蚀剂层14; 在从镀覆抗蚀剂层14暴露的化学镀铜层12上形成电解镀铜层16; 除去电镀抗蚀剂14的层，以暴露除了形成电解镀铜层16的部分之外的无电镀铜层12; 并且通过使用由含有硫酸，过氧化氢和Cu螯合剂的混合水溶液组成的蚀刻溶液除去暴露的化学镀铜层12。

公开(公告)号：US20090206471A1

公开(公告)日：2009-08-20

申请号：US12385814

申请日：2009-04-21

申请人： Masahiro Sunohara ,  Kei Murayama ,  Toshinori Koyama ,  Kazutaka Kobayashi ,  Mitsutoshi Higashi

发明人： Masahiro Sunohara ,  Kei Murayama ,  Toshinori Koyama ,  Kazutaka Kobayashi ,  Mitsutoshi Higashi

IPC分类号： H01L23/48

CPC分类号： H01L23/5383 ,  H01L21/563 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81205 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/82039 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05644 ,  H01L2224/05155

摘要： An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.

摘要翻译： 本发明的电子零件包装结构体包括具有布线图案的布线基板，形成在布线基板上的第一绝缘膜，并且在安装有电子部件的封装区域中具有开口部，电子部件具有 安装在暴露在第一绝缘膜的开口部分中的布线图案上的连接端子倒装芯片，用于覆盖电子部件的第二绝缘膜，形成在布线上的第一和第二绝缘膜的预定部分中的通孔 图案和形成在第二绝缘膜上并通过通孔连接到布线图案的上部布线图案。

公开(公告)号：US07545049B2

公开(公告)日：2009-06-09

申请号：US11362189

申请日：2006-02-27

申请人： Masahiro Sunohara ,  Kei Murayama ,  Toshinori Koyama ,  Kazutaka Kobayashi ,  Mitsutoshi Higashi

发明人： Masahiro Sunohara ,  Kei Murayama ,  Toshinori Koyama ,  Kazutaka Kobayashi ,  Mitsutoshi Higashi

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5383 ,  H01L21/563 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81205 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/82039 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05644 ,  H01L2224/05155

摘要： An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.

摘要翻译： 本发明的电子零件包装结构体包括具有布线图案的布线基板，形成在布线基板上的第一绝缘膜，并且在安装有电子部件的封装区域中具有开口部，电子部件具有 安装在暴露在第一绝缘膜的开口部分中的布线图案上的连接端子倒装芯片，用于覆盖电子部件的第二绝缘膜，形成在布线上的第一和第二绝缘膜的预定部分中的通孔 图案和形成在第二绝缘膜上并通过通孔连接到布线图案的上部布线图案。

公开(公告)号：US07573135B2

公开(公告)日：2009-08-11

申请号：US11798813

申请日：2007-05-17

申请人： Masahiro Sunohara ,  Kei Murayama ,  Mitsutoshi Higashi ,  Toshinori Koyama

发明人： Masahiro Sunohara ,  Kei Murayama ,  Mitsutoshi Higashi ,  Toshinori Koyama

IPC分类号： H01L23/04 ,  H01L23/52 ,  H01L23/538 ,  H01L25/065 ,  H05K1/18

CPC分类号： H05K1/185 ,  H01L21/4857 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/81205 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/82039 ,  H01L2224/83192 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/186 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/10674 ,  H05K2203/1189 ,  H01L2924/00

摘要： The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward, forming a second resin film for covering the electronic parts, obtaining an insulation film by curing the first and second resin films by heat treatment, forming a via hole in a predetermined portion of the insulation film on the wiring pattern and the connection terminal, and forming an upper wiring pattern connected to the wiring pattern and the connection terminal through the via hole, on the insulation film.

摘要翻译： 本发明包括以下步骤：在包括布线图案的布线基板上形成未固化的第一树脂膜，在连接端子指向的状态下将未固化的第一树脂膜中的元件形成表面上的具有连接端子的电子部件 形成用于覆盖电子部件的第二树脂膜，通过热处理固化第一和第二树脂膜获得绝缘膜，在布线图案和连接端子上的绝缘膜的预定部分中形成通孔， 并且在所述绝缘膜上形成通过所述通孔连接到所述布线图案和所述连接端子的上部布线图案。

公开(公告)号：US20080123070A1

公开(公告)日：2008-05-29

申请号：US11812450

申请日：2007-06-19

申请人： Keiji Yoshizawa ,  Toshinori Koyama ,  Masatoshi Akagawa

发明人： Keiji Yoshizawa ,  Toshinori Koyama ,  Masatoshi Akagawa

IPC分类号： G03B27/42

CPC分类号： G03B27/58 ,  G03F7/70291 ,  G03F7/70358

摘要： In a patterning apparatus for forming a desired pattern on a surface of an object by exposing the surface of the object to light by using a plurality of spatial light modulation elements assigned to respective exposure areas defined along a relative moving direction of the object, predetermined areas which are on the surface of the object and are to be positioned in the vicinity of borders of the respective exposure areas exposed to light by the spatial light modulation elements are exposed to light by the spatial light modulation elements corresponding to the exposure areas, after the object is shifted in a direction perpendicular to the relative moving direction, such that the predetermined areas are positioned in the vicinity of the center parts of the exposure areas.

摘要翻译： 在通过使用分配给沿着物体的相对移动方向限定的各个曝光区域的多个空间光调制元件将物体表面曝光的对象的表面上形成期望图案的图案形成装置中，预定区域 在物体的表面上并且被定位在由空间光调制元件暴露于光的各个曝光区域的边界附近的位置，在与曝光区域相对应的空间光调制元件之后被曝光 物体沿垂直于相对移动方向的方向移动，使得预定区域位于曝光区域的中心部分附近。

公开(公告)号：US07307691B2

公开(公告)日：2007-12-11

申请号：US10974327

申请日：2004-10-27

申请人： Kazunari Sekigawa ,  Toshinori Koyama ,  Kazutaka Kobayashi ,  Masatoshi Akagawa

发明人： Kazunari Sekigawa ,  Toshinori Koyama ,  Kazutaka Kobayashi ,  Masatoshi Akagawa

IPC分类号： G03B27/46 ,  G03B27/42

CPC分类号： G03F7/70283 ,  G03F7/70291 ,  H05K3/0002 ,  H05K3/0005 ,  H05K3/0082

摘要： A direct exposure system comprises: a data mask that is a data object including drawing data; and a control mask that is a data object including at least one logical layer in which information about exposure conditions applied according to regions on a substrate is specified, and performs a direct exposure process using integrated data generated by combining the data mask with the control mask.

摘要翻译： 直接曝光系统包括：作为包括绘图数据的数据对象的数据掩模; 以及作为包括至少一个逻辑层的控制掩模，所述至少一个逻辑层指定了根据基板上的区域应用的关于曝光条件的信息，并且使用通过将数据掩模与控制掩模组合而生成的积分数据进行直接曝光处理 。

公开(公告)号：US20070224731A1

公开(公告)日：2007-09-27

申请号：US11798814

申请日：2007-05-17

申请人： Masahiro Sunohara ,  Kei Murayama ,  Mitsutoshi Higashi ,  Toshinori Koyama

发明人： Masahiro Sunohara ,  Kei Murayama ,  Mitsutoshi Higashi ,  Toshinori Koyama

IPC分类号： H01L21/02

CPC分类号： H05K1/185 ,  H01L21/4857 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/81205 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/82039 ,  H01L2224/83192 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/186 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/10674 ,  H05K2203/1189 ,  H01L2924/00

摘要： The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward, forming a second resin film for covering the electronic parts, obtaining an insulation film by curing the first and second resin films by heat treatment, forming a via hole in a predetermined portion of the insulation film on the wiring pattern and the connection terminal, and forming an upper wiring pattern connected to the wiring pattern and the connection terminal through the via hole, on the insulation film.

公开(公告)号：US06759600B2

公开(公告)日：2004-07-06

申请号：US10124548

申请日：2002-04-17

申请人： Toshinori Koyama ,  Noritaka Katagiri

发明人： Toshinori Koyama ,  Noritaka Katagiri

IPC分类号： H05K111

CPC分类号： H05K3/4632 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/036 ,  H05K3/423 ,  H05K3/4617 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/068 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165

摘要： A multilayer wiring board comprising a plurality of conductor patterns stacked with an insulating layer composed of a thermosetting resin interposed between adjacent conductor patterns, wherein the insulating layers are each formed of a pair of film-like thermosetting resin layers and a resin film having a lower coefficient of linear expansion than, and sandwiched between, the thermosetting resin layers, and wherein the electrical connection between the stacked conductor patterns is established by vias formed through the insulating layers. A method of fabricating such a multilayer wiring board is also disclosed.

摘要翻译： 一种多层布线基板，包括多个导体图案，所述多个导体图案层叠有介于相邻导体图案之间的由热固性树脂构成的绝缘层，其中所述绝缘层各自由一对膜状热固性树脂层和具有较低 线性膨胀系数高于并夹在热固性树脂层之间，并且其中层叠导体图案之间的电连接由通过绝缘层形成的通孔建立。 还公开了一种制造这种多层布线板的方法。