公开(公告)号：US3945347A

公开(公告)日：1976-03-23

申请号：US406927

申请日：1973-10-16

申请人： Toyoki Takemoto ,  Hiroshi Kuroda

发明人： Toyoki Takemoto ,  Hiroshi Kuroda

IPC分类号： H01L21/28 ,  H01L21/027 ,  H01L21/285 ,  H01L23/29 ,  H01L23/522 ,  B01J17/00

CPC分类号： H01L23/293 ,  H01L21/0272 ,  H01L23/522 ,  H01L2924/0002

摘要： In a method of making integrated circuits, prior to vapor deposition of metal layers on an insulating layer for interconnection, each opening on the insulating layer is filled with an embedded metal layer in order to smoothen the surface to be vapor deposited and to avoid undesirable thin parts of the vapor deposited metal layer at the step between the lower part in the opening and the elevated part on the insulating layer. The filling of the embedded metal layer in each opening is made by a first step of coating a metal layer on the whole surface of the principal face of the semi-conductor, which surface is coated by the insulating layer with specified openings and further by a photoresist layer which has been used for etching the insulating layer to form said openings and is left covering said insulating layer, and by the subsequent step of applying a photoresist removing liquid on the face to remove the photoresist layer and the part of metal layer still remaining on the photoresist layer.

摘要翻译： 在制造集成电路的方法中，在将金属层蒸镀在用于互连的绝缘层上之前，绝缘层上的每个开口都填充有嵌入的金属层，以平滑待蒸汽沉积的表面，并避免不希望的薄 在开口的下部与绝缘层上的升高部之间的台阶处，蒸镀金属层的部分。 每个开口中的嵌入金属层的填充是通过在半导体的主面的整个表面上涂覆金属层的第一步骤制成的，该表面被具有特定开口的绝缘层涂覆，并且进一步由 已经用于蚀刻绝缘层以形成所述开口并且覆盖所述绝缘层的光致抗蚀剂层，并且通过在表面上施加光致抗蚀剂去除液体以除去光致抗蚀剂层并且金属层的一部分仍然残留的后续步骤 在光刻胶层上。

公开(公告)号：US4814287A

公开(公告)日：1989-03-21

申请号：US82212

申请日：1987-08-06

申请人： Toyoki Takemoto ,  Kenji Kawakita ,  Hiroyuki Sakai

发明人： Toyoki Takemoto ,  Kenji Kawakita ,  Hiroyuki Sakai

IPC分类号： H01L27/00 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8236 ,  H01L27/06 ,  H01L27/088 ,  H01L21/76 ,  H01L21/95

CPC分类号： H01L21/743 ,  H01L21/76245 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/7627 ,  H01L21/76281

摘要： A method of manufacturing a semiconductor integrated circuit device of the bipolar type of the MOS type or an integration of the two types having high integration and high performance, in which the circuit includes a first device region of which the side surface and entire region of the lower portion of the active region are made of silicon oxide and a second device region of which the side surface and a part of the lower portion of the active region are made of silicon oxide. According to the present invention, a transistor whose bottom portion is opened and a transistor whose bottom portion is not opened can be freely provided on a substrate, thereby dividing the transistors into a transistor to which a voltage can be supplied from the substrate and a transistor to which the voltage can not be supplied from the substrate, so that the wiring which has been conventionally needed can be reduced. In addition, in such transistors which are completely separated, the parasitic effect with the circumference is completely prevented so that excellent characteristics can be provided.

摘要翻译： 一种制造双极型MOS型半导体集成电路器件的方法或者具有高集成度和高​​性能的两种类型的集成方法，其中电路包括第一器件区域，其中第一器件区域的侧表面和整个区域 有源区的下部由氧化硅制成，其第二器件区的有源区的侧表面和下部的一部分由氧化硅制成。 根据本发明，底部开放的晶体管和其底部未打开的晶体管可以自由地设置在基板上，从而将晶体管分成从基板提供电压的晶体管和晶体管 不能从基板供给电压，从而可以减少传统上需要的布线。 此外，在完全分离的这种晶体管中，完全防止与圆周的寄生效应，从而可以提供优异的特性。

公开(公告)号：US4459496A

公开(公告)日：1984-07-10

申请号：US251966

申请日：1981-04-03

申请人： Haruyasu Yamada ,  Toyoki Takemoto ,  Tadao Komeda ,  Tsutomu Fujita ,  Yuichi Hirofuji ,  Hiroyuki Sakai

发明人： Haruyasu Yamada ,  Toyoki Takemoto ,  Tadao Komeda ,  Tsutomu Fujita ,  Yuichi Hirofuji ,  Hiroyuki Sakai

IPC分类号： H03K19/091 ,  H03K19/092

CPC分类号： H03K19/091

摘要： In a stacked, multilayer IIL (integrated injection logic) circuit, with which power consumption can be significantly reduced, a discharging circuit constructed of an IIL constant-current circuit or of a resistor is provided for one of transistors which are used for shifting the level of a signal from an IIL circuit of a top layer to an IIL circuit of a bottom layer, so that signal transmission therebetween is prevented from deterioration. A charging circuit may be added to another transistor, while a diode may be interposed between these transistors. Additional diodes may be interposed between adjacent layers for speeding up the signal transmission from one layer to another upper layer.

摘要翻译： 在堆叠的多层IIL（集成注入逻辑）电路中，功率消耗可以显着降低，由用于移位电平的晶体管之一提供由IIL恒流电路或电阻构成的放电电路 从顶层的IIL电路到底层的IIL电路的信号，从而防止它们之间的信号传输劣化。 充电电路可以被添加到另一个晶体管，而二极管可以插在这些晶体管之间。 可以在相邻层之间插入附加的二极管，以加速从一个层到另一个上层的信号传输。

公开(公告)号：US5066602A

公开(公告)日：1991-11-19

申请号：US295380

申请日：1989-01-10

申请人： Toyoki Takemoto ,  Tadao Komeda ,  Haruyasu Yamada ,  Tsutomu Fujita

发明人： Toyoki Takemoto ,  Tadao Komeda ,  Haruyasu Yamada ,  Tsutomu Fujita

IPC分类号： H01L21/74 ,  H01L21/761 ,  H01L21/8228 ,  H01L27/02 ,  H01L27/06 ,  H01L27/082 ,  H01L27/092

CPC分类号： H01L27/0244 ,  H01L21/74 ,  H01L21/761 ,  H01L21/82285 ,  H01L27/0623 ,  H01L27/0826 ,  H01L27/0922 ,  Y10S148/009 ,  Y10S148/151

摘要： In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.FE transistor, high speed vertical npn transistor, cross-over devices, p-channel and/or n-channel MOS transistors can be formed within limited manufacturing steps.

公开(公告)号：US4441198A

公开(公告)日：1984-04-03

申请号：US275848

申请日：1981-06-22

申请人： Jun Shibata ,  Haruyasu Yamada ,  Toshiki Mori ,  Toyoki Takemoto

发明人： Jun Shibata ,  Haruyasu Yamada ,  Toshiki Mori ,  Toyoki Takemoto

IPC分类号： G11C19/00 ,  H03M1/00 ,  G11C19/28 ,  H03K19/173

CPC分类号： G11C19/00 ,  H03M1/38

摘要： A first logic circuit comprises coupling gate circuits driven by clock pulses of different phases, flip-flop circuits cascade-connected via the coupling gate circuits and feedback circuits for feeding back the outputs of the flip-flop circuits to the preceding stage flip-flop circuits, and generates pulse sequences of different phases. A second logic circuit further comprises latch circuits one for each of the flip-flop circuits, driven by the pulse sequences generated by the first logic circuit. Those logic circuits are useful to a successive approximation register of a successive approximation A/D converter.

摘要翻译： 第一逻辑电路包括耦合由不同相位的时钟脉冲驱动的门电路，经由耦合门电路级联的触发器电路和用于将触发器电路的输出反馈到前级触发电路的反馈电路 并产生不同相位的脉冲序列。 第二逻辑电路还包括由用于由第一逻辑电路产生的脉冲序列驱动的每个触发器电路的锁存电路。 这些逻辑电路对逐次逼近A / D转换器的逐次逼近寄存器是有用的。

公开(公告)号：US4685198A

公开(公告)日：1987-08-11

申请号：US758962

申请日：1985-07-25

申请人： Kenji Kawakita ,  Noboru Nomura ,  Toyoki Takemoto

发明人： Kenji Kawakita ,  Noboru Nomura ,  Toyoki Takemoto

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L29/06

CPC分类号： H01L21/76264 ,  H01L21/762 ,  H01L21/763 ,  H01L21/76281 ,  H01L21/76283 ,  Y10S148/05 ,  Y10S148/115 ,  Y10S438/973

摘要： Disclosed is a method of isolating a transistor perfectly by employing a selective oxidation technology (LOCOS technology). More particularly, vertical openings are formed in the surface of {100} silicon substrate, and oxidation resistant films are formed of this surface and in part of the side walls of these openings. In succession, by etching with an etchant having an orientation anisotropy, dents are formed at high precision in the side walls of the openings. By oxidizing using the oxidation resistant film as the mask, an oxide film growing out from a dent in the opening side wall is connected with another oxide film growing out from an adjacent dent. The transistor thus formed in the active region of the silicon electrically isolated from the substrate is small in parasitic capacitance and may be formed into a small size, so that it possesses the features suited to VLSI, that is, high speed, low power consumption, and processability to high density integration.

摘要翻译： 公开了通过采用选择氧化技术（LOCOS技术）将晶体管完全隔离的方法。 更具体地，在{100}硅衬底的表面中形成垂直开口，并且由该表面和这些开口的一部分侧壁形成抗氧化膜。 相继地，通过用具有取向各向异性的蚀刻剂进行蚀刻，在开口的侧壁中以高精度形成凹痕。 通过使用抗氧化膜作为掩模进行氧化，从开口侧壁中的凹陷生长的氧化膜与从相邻凹坑生长的另一氧化膜连接。 因此，在与衬底电隔离的硅的有源区中形成的晶体管的寄生电容小，并且可以形成为小尺寸，使得其具有适合于VLSI的特征，即高速度，低功耗， 和可加工性的高密度集成。

公开(公告)号：US4615746A

公开(公告)日：1986-10-07

申请号：US652096

申请日：1984-09-19

申请人： Kenji Kawakita ,  Hiroyuki Sakai ,  Toyoki Takemoto

发明人： Kenji Kawakita ,  Hiroyuki Sakai ,  Toyoki Takemoto

IPC分类号： H01L21/22 ,  H01L21/762 ,  H01L21/225 ,  H01L21/302

CPC分类号： H01L21/22 ,  H01L21/76264 ,  H01L21/76281

摘要： A method of fabricating a semiconductor device comprises the steps of forming oxidation-resistive films on the surface and sides of a protrusion formed on a semiconductor substrate, forming grooves at the bottom of the sides of the protrusion, forming highly doped impurity diffusion regions in the groove surfaces, and subjecting the grooves to selective oxidation to form an oxide film under the bottom of the protrusion while a highly doped impurity diffusion region is formed, and forming a device in the protrusion.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在形成在半导体衬底上的突起的表面和侧面上形成耐氧化膜，在突起的侧面的底部形成凹槽，在其中形成高掺杂杂质扩散区 凹槽表面，并且使凹槽经受选择性氧化，以在突起的底部形成氧化膜，同时形成高度掺杂的杂质扩散区，并在突起中形成器件。

公开(公告)号：US4496935A

公开(公告)日：1985-01-29

申请号：US368814

申请日：1982-04-15

申请人： Michihiro Inoue ,  Akira Matsuzawa ,  Toyoki Takemoto

发明人： Michihiro Inoue ,  Akira Matsuzawa ,  Toyoki Takemoto

IPC分类号： H03M1/36 ,  H03M1/00 ,  H03K13/175

CPC分类号： H03M1/06 ,  H03M1/361

摘要： A parallel type analog-digital converter having a plural number (1023) of comparators, a first voltage divider comprising a plural number (1023) of resistors (R.sub.1 to R.sub.1023) connected in series across positive and negative terminals of a power source thereby feeding reference voltages from the junction points to the comparators, the apparatus further comprisesa second voltage divider comprising a second plural number (8) of resistors (r.sub.1, r.sub.2 . . . r.sub.8) connected in series across the voltage feeding terminals thereby feeding input voltages to input terminals of the current amplifiers D.sub.1, D.sub.2 . . . D.sub.8, the output of which is given to the corresponding junction points of the first voltage divider, thereby to equalize voltages of said first voltage divider with voltages of corresponding junction points of said second voltage divider.

摘要翻译： 一种具有多个（1023）比较器的并联型模拟数字转换器，包括多个（1023）电阻器（R1至R1023）的第一分压器，其串联连接在电源的正极和负极端子上，从而馈送基准 电压从结点到比较器，该装置还包括一个第二分压器，包括在电压馈电端子上串联连接的第二多个（8）电阻器（r1，r2 ... r8），从而将输入电压馈送到输入端 电流放大器D1，D2的端子。 。 。 D8，其输出被提供给第一分压器的对应连接点，从而使所述第一分压器的电压与所述第二分压器的对应连接点的电压相等。

公开(公告)号：US5661066A

公开(公告)日：1997-08-26

申请号：US965967

申请日：1991-04-02

申请人： Toyoki Takemoto ,  Haruyasu Yamada ,  Tsutomu Fujita ,  Tadao Komeda

发明人： Toyoki Takemoto ,  Haruyasu Yamada ,  Tsutomu Fujita ,  Tadao Komeda

IPC分类号： H01L21/8222 ,  H01L27/02 ,  H01L27/06 ,  H01L29/8605 ,  H01L29/93 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/0233 ,  H01L21/8222 ,  H01L27/0244 ,  H01L27/0647 ,  H01L29/8605 ,  H01L29/93

摘要： In an integrated circuit comprising an IIL and a high frequency npn bipolar transistor which has a deep p.sup.- -type base region 45 for its inverted npn output transistors, circuit elements such as a resistor part R, a capacitor part C, a diode part D and an isolated crossing connection part Cr are provided with deep p.sup.- -type regions 54, 54', 65', 71 and 82 which are formed at the same time with the p.sup.- -type region 45 in the IIL, and thereby, reliability of the circuit elements as well as characteristic thereof are improved, thereby further improving manufacturing yields.

摘要翻译： 在包括IIL和高频npn双极晶体管的集成电路中，其具有用于其反相npn输出晶体管的深p型基极区45，电路元件如电阻器部分R，电容器部分C，二极管部分D 并且隔离交叉连接部分Cr设置有与IIL中的p型区域45同时形成的深P型区域54,54'，65'，71和82，从而可靠性 的电路元件及其特性得到改善，从而进一步提高了制造成品率。

公开(公告)号：US4563227A

公开(公告)日：1986-01-07

申请号：US660255

申请日：1984-10-12

申请人： Hiroyuki Sakai ,  Kenji Kawakita ,  Tsutomu Fujita ,  Toyoki Takemoto

发明人： Hiroyuki Sakai ,  Kenji Kawakita ,  Tsutomu Fujita ,  Toyoki Takemoto

IPC分类号： H01L21/762 ,  H01L21/38 ,  H01L21/467

CPC分类号： H01L21/76232 ,  H01L21/762

摘要： The invention provides a method for manufacturing a semiconductor device, wherein a semiconductor substrate is vertically etched to form a groove, antioxidant insulating films are formed on the side walls of the groove, and local oxidation is performed. Lateral extrusion of an oxide film which is a so-called bird's beak and a projection of the oxide film which is a so-called bird's head are substantially eliminated. As a result, the active region of the transistor, that is, the element formation region may not be narrowed, providing high packing density and high precision. Furthermore, the surface of the semiconductor substrate is flattened to prevent short-circuiting and disconnections of wiring layers. Stable manufacturing process provides a high yield of the semiconductor device. Electrical characteristics of the semiconductor device are greatly improved.

摘要翻译： 本发明提供一种制造半导体器件的方法，其中半导体衬底被垂直蚀刻以形成沟槽，在沟槽的侧壁上形成抗氧化绝缘膜，并进行局部氧化。 基本上消除了所谓的鸟喙的氧化膜的侧向挤出和所谓的鸟头的氧化膜的突起。 结果，晶体管的有源区，即元件形成区域可能不会变窄，提供高的堆积密度和高精度。 此外，半导体衬底的表面被平坦化以防止布线层的短路和断开。 稳定的制造工艺提供了高产量的半导体器件。 半导体器件的电气特性大大提高。