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公开(公告)号：US08179695B2
公开(公告)日：2012-05-15
申请号：US12783478
申请日：2010-05-19
申请人： Uei-Ming Jow , Chin-Sun Shyu , Chang-Sheng Chen , Min-Lin Lee , Shinn-Juh Lai
发明人： Uei-Ming Jow , Chin-Sun Shyu , Chang-Sheng Chen , Min-Lin Lee , Shinn-Juh Lai
IPC分类号： H05K9/00
CPC分类号： H05K1/0218 , H05K1/0224 , H05K1/0237 , H05K1/025 , H05K1/162 , H05K1/165 , H05K1/167 , H05K2201/0792 , H05K2201/09672
摘要： A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.
摘要翻译： 提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。 接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。 因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。 此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。
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公开(公告)号：US08058956B2
公开(公告)日：2011-11-15
申请号：US12801673
申请日：2010-06-21
CPC分类号： H05K1/0251 , H01L23/66 , H01L2223/6616 , H01L2223/6638 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H01P5/02 , H05K1/0222 , H05K1/0245 , H05K1/115 , H05K1/116 , H05K3/429 , H05K2201/09236 , H05K2201/09454 , H05K2201/09618 , H05K2201/09627 , H05K2201/09809 , H05K2201/09845 , H01L2924/00
摘要： A high frequency and wide band impedance matching via is provided, applicable to multi-layer printed circuit boards, for example. The multi-layer circuit board may include several signal transmission traces, several ground layers, signal transmission vias and ground vias. The signal transmission traces and the ground layers may be sited on different circuit layers, and each signal transmission trace may be opposite to one of the ground layers. The signal transmission vias may be connected between the signal transmission traces. The ground vias may be connected between the ground layers. The ground vias may be opposite to the signal transmission vias, and the ground vias corresponding to the signal transmission vias may be sited to stabilize the characteristic impedance of the transmission traces.
摘要翻译： 提供了高频和宽带阻抗匹配通孔，例如适用于多层印刷电路板。 多层电路板可以包括几个信号传输迹线，几个接地层，信号传输通路和接地通孔。 信号传输迹线和接地层可以位于不同的电路层上，并且每个信号传输迹线可以与一个接地层相反。 信号传输通孔可以连接在信号传输迹线之间。 接地通孔可以连接在接地层之间。 接地通孔可能与信号传输通孔相反，并且可能选择对应于信号传输通孔的接地通孔来稳定传输迹线的特性阻抗。
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公开(公告)号：US07529103B2
公开(公告)日：2009-05-05
申请号：US11438363
申请日：2006-05-23
申请人： Chang-Sheng Chen , Uei-Ming Jow , Ying-Jiunn Lai , Chin-Sun Shyu
发明人： Chang-Sheng Chen , Uei-Ming Jow , Ying-Jiunn Lai , Chin-Sun Shyu
IPC分类号： H05K1/14
CPC分类号： H05K1/162 , H03H7/09 , H03H7/1775 , H03H2001/0085 , H05K3/4626 , H05K3/4688 , H05K2201/09236 , H05K2201/09672
摘要： A multi-layered printed circuit board embedded with a filter, the multi-layered printed circuit board using a composite multi-layered printed circuit board formed of at least a high dielectric material stacked with at least a low dielectric material. A plurality of serial or parallel capacitors are disposed in the composite multi-layered printed circuit board so as to form a filter. At least one capacitor is an interdigital capacitor disposed on a low dielectric material. Metal electrodes of the interdigital capacitor are located on the same plane such that the area of the metal electrodes or the spacing between the metal electrodes can be adjusted in advance to precisely control the electrical properties such as the center frequency and the transmission loss of the filter. Problems resulting from alignment errors caused in manufacturing the composite multi-layered printed circuit board can also be prevented.
摘要翻译： 嵌入滤光器的多层印刷电路板，使用由至少由至少低介电材料层叠的高介电材料形成的复合多层印刷电路板的多层印刷电路板。 多个串联或并联电容器设置在复合多层印刷电路板中以形成滤波器。 至少一个电容器是设置在低电介质材料上的叉指电容器。 叉指电容器的金属电极位于同一平面上，使得金属电极的面积或金属电极之间的间隔可以预先调整以精确地控制诸如滤波器的中心频率和传输损耗之类的电气特性 。 也可以防止在制造复合多层印刷电路板时引起的对准误差所引起的问题。
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公开(公告)号：US07446995B2
公开(公告)日：2008-11-04
申请号：US11362115
申请日：2006-02-27
摘要： A symmetrical capacitor includes at least a first metal layer and a second metal layer. Each of the metal layers has a first electrode plate and a second electrode plate separated by a predetermined distance. The first electrode plates on the metal layers are symmetrical, and the second electrode plates on the metal layers are symmetrical. Given the symmetrical structure of the capacitor, the output ports of the capacitor have the same electrical features. Therefore, there will not be a direction problem when the capacitor is used, and the symmetrical electrical features are improved.
摘要翻译： 对称电容器包括至少第一金属层和第二金属层。 每个金属层具有分隔预定距离的第一电极板和第二电极板。 金属层上的第一电极板是对称的，金属层上的第二电极板是对称的。 给定电容器的对称结构，电容器的输出端口具有相同的电气特性。 因此，当使用电容器时不会有方向问题，并且改善对称的电气特征。
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公开(公告)号：US20070183131A1
公开(公告)日：2007-08-09
申请号：US11451292
申请日：2006-06-12
申请人： Uei-Ming Jow , Chin-Sun Shyu , Chang-Sheng Chen , Min-Lin Lee , Shinn-Juh Lai
发明人： Uei-Ming Jow , Chin-Sun Shyu , Chang-Sheng Chen , Min-Lin Lee , Shinn-Juh Lai
CPC分类号： H05K1/0218 , H05K1/0224 , H05K1/0237 , H05K1/025 , H05K1/162 , H05K1/165 , H05K1/167 , H05K2201/0792 , H05K2201/09672
摘要： A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.
摘要翻译： 提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。 接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。 因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。 此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。
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公开(公告)号：US20070025052A1
公开(公告)日：2007-02-01
申请号：US11362115
申请日：2006-02-27
IPC分类号： H01G4/005
摘要： A symmetrical capacitor includes at least a first metal layer and a second metal layer. Each of the metal layers has a first electrode plate and a second electrode plate separated by a predetermined distance. The first electrode plates on the metal layers are symmetrical, and the second electrode plates on the metal layers are symmetrical. Given the symmetrical structure of the capacitor, the output ports of the capacitor have the same electrical features. Therefore, there will not be a direction problem when the capacitor is used, and the symmetrical electrical features are improved.
摘要翻译： 对称电容器包括至少第一金属层和第二金属层。 每个金属层具有分隔预定距离的第一电极板和第二电极板。 金属层上的第一电极板是对称的，金属层上的第二电极板是对称的。 给定电容器的对称结构，电容器的输出端口具有相同的电气特性。 因此，当使用电容器时不会有方向问题，并且改善对称的电气特征。
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公开(公告)号：US07068122B2
公开(公告)日：2006-06-27
申请号：US10954107
申请日：2004-09-28
CPC分类号： H01P5/10
摘要： A miniaturized multi-layer balun includes a pair of capacitive elements, at least one section of broadside coupled lines connected in series to an unbalanced and two balanced ports through a pair of transmission lines. Each section has first and second coupled lines. A ground connection is located between two central second coupled lines, and connected to a ground. By means of a multi-layer structure and the addition of a ground connection, the balun of the invention can be fabricated with five conductor layers. This not only greatly decreases the size of the balun device, but also enhances the stability of the device. From the measured return loss and differences in magnitude and phase to the frequency response, it shows that the balun of the invention has good impedance match.
摘要翻译： 小型化多层平衡 - 不平衡变换器包括一对电容元件，通过一对传输线与至不平衡端口和两个平衡端口串联连接的至少一个宽边耦合线段。 每个部分具有第一和第二耦合线。 接地连接位于两个中央第二耦合线之间，并连接到地面。 通过多层结构和添加接地连接，本发明的平衡 - 不平衡变换器可以用五个导体层制造。 这不仅大大减小了平衡 - 转换装置的尺寸，而且还增强了装置的稳定性。 从测量的回波损耗和幅度和相位的差异到频率响应，表明本发明的平衡 - 不平衡变换器具有良好的阻抗匹配。
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公开(公告)号：US20060066415A1
公开(公告)日：2006-03-30
申请号：US10954107
申请日：2004-09-28
IPC分类号： H01P5/10
CPC分类号： H01P5/10
摘要： A miniaturized multi-layer balun includes a pair of capacitive elements, at least one section of broadside coupled lines connected in series to a unbalanced and two balanced ports through a pair of transmission lines. Each section has first and second coupled lines. A ground connection is located between two central second coupled lines, and connected to a ground. By means of a multi-layer structure and the addition of a ground connection, the balun of the invention can be fabricated with five conductor layers. This not only greatly decreases the size of the balun device, but also enhances the stability of the device. From the measured return loss and differences in magnitude and phase to the frequency response, it shows that the balun of the invention has good impedance match.
摘要翻译： 小型化多层平衡 - 不平衡变换器包括一对电容元件，通过一对传输线与至少一个不平衡端口和两个平衡端口串联连接的至少一个宽边耦合线段。 每个部分具有第一和第二耦合线。 接地连接位于两个中央第二耦合线之间，并连接到地面。 通过多层结构和添加接地连接，本发明的平衡 - 不平衡变换器可以用五个导体层制造。 这不仅大大减小了平衡 - 转换装置的尺寸，而且还增强了装置的稳定性。 从测量的回波损耗和幅度和相位的差异到频率响应，表明本发明的平衡 - 不平衡变换器具有良好的阻抗匹配。
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公开(公告)号：US07928824B2
公开(公告)日：2011-04-19
申请号：US12022967
申请日：2008-01-30
申请人： Uei-Ming Jow , Chang-Sheng Chen
发明人： Uei-Ming Jow , Chang-Sheng Chen
IPC分类号： H01F5/00
CPC分类号： H01F17/0013 , H01F17/0033 , H01F2005/006 , H01F2017/002 , H01F2017/004 , H01F2017/0053 , H01F2017/0073 , H01F2017/0086
摘要： The invention relates to a high frequency inductor device with high quality factor (Q). The inductor device comprises a substrate and a gradually sized conductive coil with a plurality of windings surrounded and disposed on the substrate. The windings comprises a first conductive segment disposed on a first surface of the substrate, a second conductive segment disposed on a second surface of the substrate, a first conductive via hole connecting the first and second conductive segments, and a second conductive via hole connecting the second conductive segment to a first conductive segment of the following winding. The length of the first conductive segment is different than that of the first conductive segment of the following winding.
摘要翻译： 本发明涉及一种高品质因数（Q）的高频电感器件。 电感器件包括衬底和逐渐尺寸的导电线圈，其中多个绕组包围并设置在衬底上。 绕组包括设置在基板的第一表面上的第一导电段，设置在基板的第二表面上的第二导电段，连接第一和第二导电段的第一导电通孔，以及连接第 第二导电段连接到以下绕组的第一导电段。 第一导电段的长度不同于以下绕组的第一导电段的长度。
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10.发明授权Film resistor embedded in multi-layer circuit board and manufacturing method thereof 有权嵌入多层电路板的薄膜电阻及其制造方法公开(公告)号：US07830241B2
公开(公告)日：2010-11-09
申请号：US11485785
申请日：2006-07-12
申请人： Ying-Jiunn Lai , Chin-Sun Shyu , Chang-Sheng Chen , Uei-Ming Jow
发明人： Ying-Jiunn Lai , Chin-Sun Shyu , Chang-Sheng Chen , Uei-Ming Jow
IPC分类号： H01C1/012
CPC分类号： H05K1/167 , H01C1/14 , H01C7/003 , H05K3/4644 , H05K2201/09509 , H05K2201/09563 , H05K2203/1453
摘要： A resistor structure embedded in a multi-layer circuit board and manufacturing method thereof are provided. Resistive material is coated on any layer among the multi-layer circuit board, and two symmetric electrodes are formed in the geometric center of the resistive material area. The two electrodes are disposed in the resistive material layer and are covered by the resistive material. And the two electrodes are led out from respective bores at the central position of the resistive electrodes, for connecting to any other metal layer. This resistor structure can avoid the unstable resistance when the coated resistor is operated at high frequency, and also avoid the formation untrimmed edges during coating that affects the precision of resistance.
摘要翻译： 提供一种嵌入多层电路板的电阻结构及其制造方法。 电阻材料涂覆在多层电路板中的任何层上，并且在电阻材料区域的几何中心形成两个对称电极。 两个电极设置在电阻材料层中并被电阻材料覆盖。 并且两个电极从电阻电极的中心位置处的各个孔引出，用于连接到任何其它金属层。 这种电阻结构可以避免涂层电阻器在高频率下运行时的不稳定电阻，并且避免了在涂层期间形成未经修整的边缘，影响电阻精度。
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