公开(公告)号：US20120168792A1

公开(公告)日：2012-07-05

申请号：US13244544

申请日：2011-09-25

申请人： Un-Byoung KANG ,  Kwang-chul CHOI ,  Jung-Hwan KIM ,  Tae Hong MIN

发明人： Un-Byoung KANG ,  Kwang-chul CHOI ,  Jung-Hwan KIM ,  Tae Hong MIN

IPC分类号： H01L33/26 ,  H01L33/38

CPC分类号： H01L33/486 ,  H01L33/0079 ,  H01L33/62 ,  H01L2224/16 ,  H01L2933/0066

摘要： In one embodiment, a heterojunction structure includes a first substrate; a second substrate comprising an electrode pad, the second substrate joined to the first substrate by an adhesive layer interposed between the first and second substrates, the first substrate and the adhesive layer having a via hole penetrating therethrough to expose a region of the electrode pad; a connection electrode disposed in the via hole and contacting the electrode pad; and an insulation layer electrically insulating the connection electrode from the first substrate. One of the first and second substrates has a thermal expansion coefficient different than a thermal expansion coefficient of the other of the first and second substrates, and at least one of the adhesive layer or the insulation layer comprises an organic material.

摘要翻译： 在一个实施例中，异质结结构包括第一衬底; 第二基板，其包括电极焊盘，所述第二基板通过插入在所述第一和第二基板之间的粘合剂层连接到所述第一基板，所述第一基板和所述粘合剂层具有贯穿其中的通孔，以暴露所述电极焊盘的区域; 连接电极，设置在所述通孔中并与所述电极焊盘接触; 以及将连接电极与第一基板电绝缘的绝缘层。 第一和第二基板中的一个具有不同于第一和第二基板中的另一个的热膨胀系数的热膨胀系数，并且粘合剂层或绝缘层中的至少一个包括有机材料。

公开(公告)号：US20140213039A1

公开(公告)日：2014-07-31

申请号：US14150906

申请日：2014-01-09

申请人： Chungsun LEE ,  Jung-Hwan KIM ,  Kwang-chul CHOI ,  Un-Byoung KANG ,  Jeon Il LEE

发明人： Chungsun LEE ,  Jung-Hwan KIM ,  Kwang-chul CHOI ,  Un-Byoung KANG ,  Jeon Il LEE

IPC分类号： H01L21/683 ,  H01L21/302

CPC分类号： H01L21/302 ,  H01L21/02057 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/92222 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2221/68368 ,  H01L21/78 ,  H01L2224/81

摘要： Methods processing substrates are provided. The method may include providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting glue layer and thermosetting release layers provided on opposing sides of the thermosetting glue layer.

摘要翻译： 提供了处理衬底的方法。 该方法可以包括在衬底和载体之间提供结合层，以将衬底粘合到载体上，在衬底被载体支撑的同时处理衬底，以及去除结合层以使衬底与载体分离。 接合层可以包括热固性胶层和设置在热固性胶层的相对侧上的热固性剥离层。

公开(公告)号：US20120049352A1

公开(公告)日：2012-03-01

申请号：US13208455

申请日：2011-08-12

申请人： Un-Byoung KANG ,  Jong-Joo Lee ,  Yong-Hoon Kim ,  Tae-Hong Min

发明人： Un-Byoung KANG ,  Jong-Joo Lee ,  Yong-Hoon Kim ,  Tae-Hong Min

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L21/60

CPC分类号： H01L23/49827 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311

摘要： A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.

摘要翻译： 多芯片封装可以包括封装衬底，插入器芯片，第一半导体芯片，散热结构和第二半导体芯片。 插入器芯片可以安装在封装衬底上。 第一半导体芯片可以安装在插入器芯片上。 第一半导体芯片的尺寸可以小于插入器芯片的尺寸。 散热结构可以布置在插入器芯片上以围绕第一半导体芯片。 散热结构可以将第一半导体芯片中的热量传递到插入器芯片。 第二半导体芯片可以安装在第一半导体芯片上。 因此，可以通过散热线将第一半导体芯片中的热量有效地传递到插入器芯片。

公开(公告)号：US20090130791A1

公开(公告)日：2009-05-21

申请号：US12274642

申请日：2008-11-20

申请人： Woon-Seong KWON ,  Tae-Je CHO ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

发明人： Woon-Seong KWON ,  Tae-Je CHO ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

IPC分类号： H01L21/00

CPC分类号： H04N5/2252 ,  H01L27/14618 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H04N5/2253 ,  H04N5/2257 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： Provided are camera modules capable of effectively shielding electromagnetic (EM) waves and methods of fabricating the same. A method of fabricating a camera module includes, preparing a first wafer including an array of lens units. Then, a second wafer including an array of image sensor CSPs (chip-scale packages) is prepared. Each of the image sensor CSPs includes an image sensor chip corresponding to one of the lens units. The first wafer is stacked on the second wafer. The first wafer and the second wafer are cut to form a trench exposing the top surface of the image sensor chip at the interface between adjacent lens units. The trench is filled with a first material used for forming a housing. The first material and the image sensor chip are cut at the interface between the adjacent lens units.

摘要翻译： 提供能够有效屏蔽电磁波（EM）波的相机模块及其制造方法。 制造相机模块的方法包括：制备包括透镜单元阵列的第一晶片。 然后，制备包括图像传感器CSP阵列（芯片级封装）的第二晶片。 图像传感器CSP中的每一个包括对应于一个透镜单元的图像传感器芯片。 第一晶片被堆叠在第二晶片上。 切割第一晶片和第二晶片以形成在相邻透镜单元之间的界面处暴露图像传感器芯片的顶表面的沟槽。 沟槽填充有用于形成壳体的第一材料。 第一材料和图像传感器芯片在相邻透镜单元之间的界面处被切割。

公开(公告)号：US20080251872A1

公开(公告)日：2008-10-16

申请号：US11831768

申请日：2007-07-31

申请人： Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

发明人： Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

IPC分类号： H01L27/12 ,  H01L21/02

CPC分类号： H01L27/14618 ,  H01L24/97 ,  H01L27/14625 ,  H01L27/14683 ,  H01L27/14685 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An image sensor package, a method of manufacturing the same, and an image sensor module including the image sensor package are provided. In the image sensor package, an image sensor chip is installed onto a depression of a transmissive substrate. An adhesive bonds the image sensor chip to the transmissive substrate and seals an Active Pixel Sensor (APS) on the image sensor chip, protecting it from fine particle contamination. An IR cutting film is disposed on the transmissive substrate to minimize the height of the image sensor package. The image sensor package is electrically connected to external connection pads in the depression. Consequently, the image sensor package has a minimum height, is not susceptible to particle contamination, and does not require expensive alignment processes during manufacturing.

摘要翻译： 提供了图像传感器封装，其制造方法和包括图像传感器封装的图像传感器模块。 在图像传感器封装中，将图像传感器芯片安装在透光性基板的凹部上。 粘合剂将图像传感器芯片粘合到透射基板上，并将图像传感器芯片上的有源像素传感器（APS）密封并保护其免受细颗粒污染。 将IR切割膜设置在透射基底上以最小化图像传感器封装的高度。 图像传感器封装电连接到凹陷中的外部连接焊盘。 因此，图像传感器封装具有最小高度，不易受到颗粒污染，并且在制造期间不需要昂贵的对准过程。

公开(公告)号：US20160233155A1

公开(公告)日：2016-08-11

申请号：US15130904

申请日：2016-04-15

申请人： Ho-Jin LEE ,  Tae-Je CHO ,  Dong-Hyeon JANG ,  Ho-Geon SONG ,  Se-Young JEONG ,  Un-Byoung KANG ,  Min-Seung YOON

发明人： Ho-Jin LEE ,  Tae-Je CHO ,  Dong-Hyeon JANG ,  Ho-Geon SONG ,  Se-Young JEONG ,  Un-Byoung KANG ,  Min-Seung YOON

IPC分类号： H01L23/498 ,  H01L23/48

CPC分类号： H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

摘要翻译： 在一个实施例中，半导体器件包括具有第一表面的半导体衬底和与第一表面相对的第二表面。 第二表面限定再分布沟槽。 基板具有贯穿其中的通孔。 半导体器件还包括设置在通孔中的贯通孔。 通孔可以包括依次形成在通孔的内壁上的通孔绝缘层，阻挡层。 通孔还可以包括邻近阻挡层的导电连接器。 半导体器件还包括形成在衬底的第二表面上的绝缘层图案。 绝缘层图案限定了暴露通孔的顶表面的区域的开口。 半导体器件包括设置在沟槽中并与通孔电连接的再分配层。 绝缘层图案与导电连接器的区域重叠。

公开(公告)号：US20090122178A1

公开(公告)日：2009-05-14

申请号：US12254354

申请日：2008-10-20

申请人： Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Woon-Seong KWON ,  Hyung-Sun JANG

发明人： Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Woon-Seong KWON ,  Hyung-Sun JANG

IPC分类号： H04N5/225

CPC分类号： H04N5/2254 ,  H01L27/14618 ,  H01L2924/0002 ,  H04N5/2253 ,  H04N5/2257 ,  H04N2007/145 ,  H01L2924/00

摘要： A camera module includes an image sensor chip, a lens structure, a transparent substrate, an adhesive portion, and a light blocking layer. The image sensor chip includes a light receiving area and a circuit area. The lens structure is positioned on the image sensor chip and configured to allow light to enter the image sensor chip. The transparent substrate is positioned between the image sensor chip and the lens structure, the transparent substrate allowing light from the lens structure to enter the light receiving area. The adhesive portion attaches the image sensor chip and the transparent substrate, and covers the circuit area. The light blocking layer is attached to the transparent substrate to block light from entering the circuit area.

摘要翻译： 相机模块包括图像传感器芯片，透镜结构，透明基板，粘合部分和遮光层。 图像传感器芯片包括光接收区域和电路区域。 透镜结构位于图像传感器芯片上并且被配置为允许光进入图像传感器芯片。 透明基板位于图像传感器芯片和透镜结构之间，透明基板允许来自透镜结构的光进入光接收区域。 粘合剂部附着图像传感器芯片和透明基板，并且覆盖电路区域。 遮光层附着到透明基板上以阻挡光线进入电路区域。

公开(公告)号：US20080169546A1

公开(公告)日：2008-07-17

申请号：US11952426

申请日：2007-12-07

申请人： Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

发明人： Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

IPC分类号： H01L23/488 ,  H01L21/56

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L27/14618 ,  H01L31/0203 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A stack type semiconductor chip package includes a first wafer mold, a protection substrate, and a second wafer mold that are stacked in a wafer level process. The first wafer mold includes a first chip having first pads and a first mold layer encapsulating the first chip. The protection substrate is placed on the first wafer mold, is mechanically bonded with the first wafer mold using a first adhesive layer, and includes wiring layers facing the first pads. The second wafer mold is placed under the first wafer mold, is mechanically bonded with the first wafer mold using a second adhesive layer, and includes a second chip having second pads, and a second mold layer encapsulating the second chip. First vias electrically connect the wiring layers of the protection substrate with the second pads. Second vias electrically connect the wiring layers of the protection substrate with external connection terminals.

摘要翻译： 堆叠型半导体芯片封装包括在晶片级工艺中堆叠的第一晶片模具，保护基板和第二晶片模具。 第一晶片模具包括具有第一焊盘的第一芯片和封装第一芯片的第一模具层。 保护基板被放置在第一晶片模具上，使用第一粘合剂层与第一晶片模具机械结合，并且包括面向第一焊盘的布线层。 第二晶片模具放置在第一晶片模具下面，使用第二粘合剂层与第一晶片模具机械结合，并且包括具有第二焊盘的第二芯片和封装第二芯片的第二模具层。 第一通孔将保护衬底的布线层与第二衬垫电连接。 第二通孔将保护基板的布线层与外部连接端子电连接。

公开(公告)号：US20160013174A1

公开(公告)日：2016-01-14

申请号：US14736247

申请日：2015-06-10

申请人： Sang-Uk HAN ,  Seungwon PARK ,  Un-Byoung KANG ,  Taeje CHO

发明人： Sang-Uk HAN ,  Seungwon PARK ,  Un-Byoung KANG ,  Taeje CHO

IPC分类号： H01L25/00 ,  H01L21/82 ,  H01L23/48 ,  H01L21/56

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/82 ,  H01L23/3128 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/00

摘要： Embodiments of the inventive concepts provide a semiconductor package and a method of fabricating the same. The method includes forming a groove to separate first semiconductor chips from each other. Forming the groove include performing a first sawing process on a bottom surface of a semiconductor substrate to cut the semiconductor substrate and a portion of a mold layer in a direction inclined with respect to the bottom surface, and performing a second sawing process to cut the mold layer in a direction substantially perpendicular to the bottom surface of the semiconductor substrate. A minimum width of the groove formed in the semiconductor substrate by the first sawing process may be greater than a width of the groove formed in the mold layer by the second sawing process.

摘要翻译： 本发明构思的实施例提供一种半导体封装及其制造方法。 该方法包括形成沟槽以将第一半导体芯片彼此分开。 形成凹槽包括在半导体衬底的底表面上执行第一锯切工艺以在相对于底表面倾斜的方向上切割半导体衬底和模具层的一部分，并且执行第二锯切工艺以切割模具 层在基本上垂直于半导体衬底的底表面的方向上。 通过第一锯切工艺在半导体衬底中形成的槽的最小宽度可以大于通过第二锯切工艺在模具层中形成的槽的宽度。

公开(公告)号：US20100019338A1

公开(公告)日：2010-01-28

申请号：US12574906

申请日：2009-10-07

申请人： Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

发明人： Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

IPC分类号： H01L25/04

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L27/14618 ,  H01L31/0203 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A stack type semiconductor chip package includes a first wafer mold, a protection substrate, and a second wafer mold that are stacked in a wafer level process. The first wafer mold includes a first chip having first pads and a first mold layer encapsulating the first chip. The protection substrate is placed on the first wafer mold, is mechanically bonded with the first wafer mold using a first adhesive layer, and includes wiring layers facing the first pads. The second wafer mold is placed under the first wafer mold, is mechanically bonded with the first wafer mold using a second adhesive layer, and includes a second chip having second pads, and a second mold layer encapsulating the second chip. First vias electrically connect the wiring layers of the protection substrate with the second pads. Second vias electrically connect the wiring layers of the protection substrate with external connection terminals.

摘要翻译： 堆叠型半导体芯片封装包括在晶片级工艺中堆叠的第一晶片模具，保护基板和第二晶片模具。 第一晶片模具包括具有第一焊盘的第一芯片和封装第一芯片的第一模具层。 保护基板被放置在第一晶片模具上，使用第一粘合剂层与第一晶片模具机械结合，并且包括面向第一焊盘的布线层。 第二晶片模具放置在第一晶片模具下面，使用第二粘合剂层与第一晶片模具机械结合，并且包括具有第二焊盘的第二芯片和封装第二芯片的第二模具层。 第一通孔将保护衬底的布线层与第二衬垫电连接。 第二通孔将保护基板的布线层与外部连接端子电连接。