公开(公告)号：US20160013174A1

公开(公告)日：2016-01-14

申请号：US14736247

申请日：2015-06-10

申请人： Sang-Uk HAN ,  Seungwon PARK ,  Un-Byoung KANG ,  Taeje CHO

发明人： Sang-Uk HAN ,  Seungwon PARK ,  Un-Byoung KANG ,  Taeje CHO

IPC分类号： H01L25/00 ,  H01L21/82 ,  H01L23/48 ,  H01L21/56

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/82 ,  H01L23/3128 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/00

摘要： Embodiments of the inventive concepts provide a semiconductor package and a method of fabricating the same. The method includes forming a groove to separate first semiconductor chips from each other. Forming the groove include performing a first sawing process on a bottom surface of a semiconductor substrate to cut the semiconductor substrate and a portion of a mold layer in a direction inclined with respect to the bottom surface, and performing a second sawing process to cut the mold layer in a direction substantially perpendicular to the bottom surface of the semiconductor substrate. A minimum width of the groove formed in the semiconductor substrate by the first sawing process may be greater than a width of the groove formed in the mold layer by the second sawing process.

摘要翻译： 本发明构思的实施例提供一种半导体封装及其制造方法。 该方法包括形成沟槽以将第一半导体芯片彼此分开。 形成凹槽包括在半导体衬底的底表面上执行第一锯切工艺以在相对于底表面倾斜的方向上切割半导体衬底和模具层的一部分，并且执行第二锯切工艺以切割模具 层在基本上垂直于半导体衬底的底表面的方向上。 通过第一锯切工艺在半导体衬底中形成的槽的最小宽度可以大于通过第二锯切工艺在模具层中形成的槽的宽度。

公开(公告)号：US20160111299A1

公开(公告)日：2016-04-21

申请号：US14967490

申请日：2015-12-14

申请人： Jeong-Kyu HA ,  Youngshin KWON ,  KwanJai LEE ,  Jae-Min JUNG ,  KyongSoon CHO ,  Sang-Uk HAN

发明人： Jeong-Kyu HA ,  Youngshin KWON ,  KwanJai LEE ,  Jae-Min JUNG ,  KyongSoon CHO ,  Sang-Uk HAN

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/78

CPC分类号： H01L21/486 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/78 ,  H01L23/145 ,  H01L23/49524 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/50 ,  H01L2924/12042 ,  H05K1/114 ,  H05K1/115 ,  H05K1/189 ,  H05K3/0052 ,  H05K3/107 ,  H05K3/42 ,  H05K2203/1545 ,  Y10T156/1052 ,  H01L2924/00

摘要： A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern.

摘要翻译： 提供包括绝缘图案的胶带包装; 绝缘图案中的通孔中的通孔接触; 从所述通孔接触延伸到所述绝缘图案的切割表面的第一互连图案; 以及连接到绝缘图案下方的通孔接点的第二互连图案。 第二互连图案平行于第一互连图案并与绝缘图案的切割表面间隔开。

公开(公告)号：US20130005088A1

公开(公告)日：2013-01-03

申请号：US13531983

申请日：2012-06-25

申请人： Sang-Uk HAN ,  Jeong-Kyu Ha ,  Youngshin Kwon ,  Seung Hwan Kim ,  KwanJai Lee

发明人： Sang-Uk HAN ,  Jeong-Kyu Ha ,  Youngshin Kwon ,  Seung Hwan Kim ,  KwanJai Lee

IPC分类号： H01L21/78

CPC分类号： H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L24/13 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/81001 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided are methods of forming semiconductor modules. The method includes forming a high polymer material layer having an adhesive property on a support substrate, adhering a semiconductor chip to the support substrate using the high polymer material layer, bonding the semiconductor chip adhered to the support substrate to a flexible panel, and removing the support substrate.

摘要翻译： 提供了形成半导体模块的方法。 该方法包括在支撑基板上形成具有粘合性的高分子材料层，使用高分子材料层将半导体芯片粘附到支撑基板上，将附着在支撑基板上的半导体芯片接合到柔性面板上， 支撑基板。

公开(公告)号：US20170330862A1

公开(公告)日：2017-11-16

申请号：US15662764

申请日：2017-07-28

申请人： Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

发明人： Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/71 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/06156 ,  H01L2224/10125 ,  H01L2224/131 ,  H01L2224/14156 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75305 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014

摘要： A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one through-silicon-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction.

公开(公告)号：US20160064357A1

公开(公告)日：2016-03-03

申请号：US14825403

申请日：2015-08-13

申请人： Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

发明人： Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/71 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/06156 ,  H01L2224/10125 ,  H01L2224/131 ,  H01L2224/14156 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75305 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014

摘要： A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one silicon-through-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction.

摘要翻译： 半导体器件至少包括沿着第一方向彼此堆叠的第一和第二半导体芯片，至少一个硅通孔（TSV），至少通过第一和第二半导体芯片的第一半导体芯片，接触焊盘 所述第一半导体芯片的所述至少一个TSV，所述接触焊盘将所述第一半导体芯片的TSV电连接到所述第二半导体芯片，以及所述第一半导体芯片上的多个虚拟焊盘，所述多个虚拟焊盘与所述第一半导体芯片间隔开 彼此并且沿着第二方向从接触焊盘接合，并且虚拟焊盘具有与沿着第一方向在相应的顶部和底部表面之间测量的接触焊盘相同的高度。

公开(公告)号：US20090085185A1

公开(公告)日：2009-04-02

申请号：US12238781

申请日：2008-09-26

申请人： Hak-Kyoon BYUN ,  Tae-Hun KIM ,  Sang-Uk HAN ,  Jung-Do LEE ,  Seon-Hyang YOU

发明人： Hak-Kyoon BYUN ,  Tae-Hun KIM ,  Sang-Uk HAN ,  Jung-Do LEE ,  Seon-Hyang YOU

IPC分类号： H01L23/538

CPC分类号： H01L25/105 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stack-type semiconductor package, a method of forming the same, and an electronic system including the same are provided. The stack-type semiconductor package includes: a lower printed circuit board having a plurality of connection bumps disposed on an upper surface of the lower printed circuit board and a plurality of lower interconnections; at least one first lower chip sequentially stacked on the lower printed circuit board and electrically connected to the plurality of lower interconnections; a lower molding resin compound disposed on the lower printed circuit board and covering the first lower chips; a double-sided wiring board bonded to the lower molding resin compound and electrically connected to the connection bumps; and an upper chip package bonded to the double-sided wiring board and having upper bumps electrically connected to an interconnection pattern of the double-sided wiring board.

摘要翻译： 提供堆叠型半导体封装，其形成方法和包括该堆叠型半导体封装的电子系统。 堆叠型半导体封装包括：下印刷电路板，其具有设置在下印刷电路板的上表面上的多个连接凸块和多个下互连; 至少一个第一下部芯片，其顺序地堆叠在所述下部印刷电路板上并电连接到所述多个下部互连; 设置在下部印刷电路板上并覆盖第一下部芯片的下部成型树脂组合物; 与下模塑树脂复合物接合并与连接凸块电连接的双面布线板; 以及上芯片封装，其结合到所述双面布线板并且具有电连接到所述双面布线板的布线图案的上凸块。