公开(公告)号：US10134858B2

公开(公告)日：2018-11-20

申请号：US15493154

申请日：2017-04-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tian Choy Gan ,  Chu-Yun Hsiao ,  Chun-Che Huang ,  Chia-Fu Hsu

IPC: H01L29/06 ,  H01L29/40 ,  H01L23/535 ,  H01L29/423 ,  H01L21/762 ,  H01L21/768 ,  H01L21/02

Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

公开(公告)号：US20180226435A1

公开(公告)日：2018-08-09

申请号：US15947853

申请日：2018-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L29/51 ,  H01L29/24 ,  H01L21/02 ,  H01L23/528 ,  H01L21/768 ,  H01L21/441

CPC classification number: H01L27/1237 ,  H01L21/02107 ,  H01L21/02323 ,  H01L21/02565 ,  H01L21/441 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/512 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: The present invention provides a method of forming a semiconductor device. First, a substrate having a first insulating layer formed thereon is provided. After forming an oxide semiconductor layer on the first insulating layer, two source/drain regions are formed on the oxide semiconductor layer. A bottom oxide layer is formed to entirely cover the source/drain regions, following by forming a high-k dielectric layer on the bottom oxide layer. Next, a thermal process is performed on the high-k dielectric layer, and a plasma treatment is performed on the high-k dielectric layer in the presence of a gas containing an oxygen element

公开(公告)号：US09754841B2

公开(公告)日：2017-09-05

申请号：US15060572

申请日：2016-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

IPC: H01L21/8238 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

公开(公告)号：US20170062484A1

公开(公告)日：2017-03-02

申请号：US14872156

申请日：2015-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L27/12 ,  H01L29/51 ,  H01L29/24 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L21/441 ,  H01L29/786 ,  H01L23/528

CPC classification number: H01L27/1237 ,  H01L21/02107 ,  H01L21/02323 ,  H01L21/02565 ,  H01L21/441 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/512 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device including a substrate, an oxide semiconductor layer, two source/drain regions, a high-k dielectric layer and a bottom oxide layer. The oxide semiconductor layer is disposed on a first insulating layer disposed on the substrate. The source/drain regions are disposed on the oxide semiconductor layer. The high-k dielectric layer covers the oxide semiconductor layer and the source structure and the drain regions. The bottom oxide layer is disposed between the high-k dielectric layer and the source/drain regions, wherein the bottom oxide layer covers the source/drain regions and the oxide semiconductor layer.

Abstract translation: 本发明提供一种半导体器件及其形成方法，半导体器件包括衬底，氧化物半导体层，两个源极/漏极区，高k电介质层和底部氧化物层。 氧化物半导体层设置在设置在基板上的第一绝缘层上。 源极/漏极区域设置在氧化物半导体层上。 高k电介质层覆盖氧化物半导体层和源极结构以及漏极区域。 底部氧化物层设置在高k电介质层和源/漏区之间，其中底部氧化物层覆盖源/漏区和氧化物半导体层。

公开(公告)号：US09196699B1

公开(公告)日：2015-11-24

申请号：US14328720

申请日：2014-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Jian-Cun Ke ,  Chun-Lung Chen ,  Lung-En Kuo

IPC: H01L21/336 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/495 ,  H01L21/28088 ,  H01L21/31116 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; depositing a liner on the gate structure and the substrate; and performing an etching process by injecting a gas comprising CH3F, O2, and He for forming a spacer adjacent to the gate structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成栅极结构; 在栅极结构和衬底上沉积衬垫; 并且通过注入包含CH 3 F，O 2和He的气体来进行蚀刻处理，以形成与栅极结构相邻的间隔物。

公开(公告)号：US20150287823A1

公开(公告)日：2015-10-08

申请号：US14275858

申请日：2014-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Cun Ke ,  Chih-Wei Yang ,  Chia-Fu Hsu

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/49 ,  H01L21/265 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/66575 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/31155 ,  H01L29/4925 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a lightly doped drain in the substrate; and performing a first implantation process for implanting fluorine ions at a tiled angle into the substrate and part of the gate structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成栅极结构; 在衬底中形成轻掺杂漏极; 以及执行用于以平铺方式将氟离子注入所述衬底和所述栅极结构的一部分的第一注入工艺。

公开(公告)号：US20150214060A1

公开(公告)日：2015-07-30

申请号：US14680078

申请日：2015-04-07

Applicant: United Microelectronics Corp.

Inventor： Jian-Cun Ke ,  Chih-Wei Yang ,  Kun-Yuan Lo ,  Chia-Fu Hsu ,  Shao-Wei Wang

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在高k电介质层上形成第一底部阻挡金属（BBM）层; 进行热处理; 去除第一个BBM层; 以及在所述高k电介质层上形成第二BBM层。

公开(公告)号：US09773922B1

公开(公告)日：2017-09-26

申请号：US15336819

申请日：2016-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Hsieh Lin ,  Chia-Fu Hsu ,  Bei-Zhun Syu

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/10 ,  H01L29/78 ,  H01L27/1158

CPC classification number: H01L29/7827 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/1037 ,  H01L29/7926

Abstract: A memory device includes: a substrate; a channel layer on the substrate, in which the channel layer includes a T-shape having a horizontal portion with a first end and a second end and a vertical portion having a third end; a gate structure on a side of the vertical portion; an oxide-nitride-oxide (ONO) layer between the gate structure and the vertical portion; a source region on the first end of the horizontal portion; and a drain region on the third end of the vertical portion.

公开(公告)号：US09698059B2

公开(公告)日：2017-07-04

申请号：US14686787

申请日：2015-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tian Choy Gan ,  Chu-Yun Hsiao ,  Chia-Fu Hsu

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/265 ,  H01L27/092

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/66537 ,  H01L29/66545

Abstract: The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.

公开(公告)号：US20170092771A1

公开(公告)日：2017-03-30

申请号：US14953036

申请日：2015-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu ,  Xu Yang Shen ,  ZHIBIAO ZHOU ,  Qinggang Xing

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, an interconnect structure, and an oxide semiconductor structure. The substrate has a first region and a second region. The interconnect structure is disposed on the substrate, in the first region. The oxide semiconductor structure is disposed over a hydrogen blocking layer, in the second region of the substrate.