公开(公告)号：US20160104786A1

公开(公告)日：2016-04-14

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/092 ,  H01L21/28 ,  H01L21/321 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US20150069534A1

公开(公告)日：2015-03-12

申请号：US14023475

申请日：2013-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Cun Ke ,  Chih-Wei Yang ,  Kun-Yuan Lo ,  Chia-Fu Hsu ,  Shao-Wei Wang

IPC: H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在高k电介质层上形成第一底部阻挡金属（BBM）层; 进行热处理; 去除第一个BBM层; 以及在所述高k电介质层上形成第二BBM层。

公开(公告)号：US09754841B2

公开(公告)日：2017-09-05

申请号：US15060572

申请日：2016-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

IPC: H01L21/8238 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

公开(公告)号：US09196699B1

公开(公告)日：2015-11-24

申请号：US14328720

申请日：2014-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Jian-Cun Ke ,  Chun-Lung Chen ,  Lung-En Kuo

IPC: H01L21/336 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/495 ,  H01L21/28088 ,  H01L21/31116 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; depositing a liner on the gate structure and the substrate; and performing an etching process by injecting a gas comprising CH3F, O2, and He for forming a spacer adjacent to the gate structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成栅极结构; 在栅极结构和衬底上沉积衬垫; 并且通过注入包含CH 3 F，O 2和He的气体来进行蚀刻处理，以形成与栅极结构相邻的间隔物。

公开(公告)号：US20150287823A1

公开(公告)日：2015-10-08

申请号：US14275858

申请日：2014-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Cun Ke ,  Chih-Wei Yang ,  Chia-Fu Hsu

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/49 ,  H01L21/265 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/66575 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/31155 ,  H01L29/4925 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a lightly doped drain in the substrate; and performing a first implantation process for implanting fluorine ions at a tiled angle into the substrate and part of the gate structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成栅极结构; 在衬底中形成轻掺杂漏极; 以及执行用于以平铺方式将氟离子注入所述衬底和所述栅极结构的一部分的第一注入工艺。

公开(公告)号：US20150214060A1

公开(公告)日：2015-07-30

申请号：US14680078

申请日：2015-04-07

Applicant: United Microelectronics Corp.

Inventor： Jian-Cun Ke ,  Chih-Wei Yang ,  Kun-Yuan Lo ,  Chia-Fu Hsu ,  Shao-Wei Wang

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在高k电介质层上形成第一底部阻挡金属（BBM）层; 进行热处理; 去除第一个BBM层; 以及在所述高k电介质层上形成第二BBM层。

公开(公告)号：US09385206B2

公开(公告)日：2016-07-05

申请号：US14919738

申请日：2015-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Jian-Cun Ke ,  Chun-Lung Chen ,  Lung-En Kuo

IPC: H01L29/76 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/495 ,  H01L21/28088 ,  H01L21/31116 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the bottom of the spacer includes a tapered profile and the tapered profile comprises a convex curve.

Abstract translation: 公开了一种半导体器件。 半导体器件包括衬底，衬底上的栅极结构和与栅极结构相邻的间隔物，其中间隔物的底部包括锥形轮廓，并且锥形轮廓包括凸曲线。

公开(公告)号：US09349822B2

公开(公告)日：2016-05-24

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/321 ,  H01L27/092

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US20160093536A1

公开(公告)日：2016-03-31

申请号：US14520342

申请日：2014-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/423 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Abstract translation: 本发明提供一种集成电路，其包括衬底，第一晶体管，第二晶体管和第三晶体管。 第一晶体管具有包括第一底部阻挡层，第一功函数金属层和第一金属层的第一金属栅极。 第二晶体管具有包括第二底部阻挡层，第二功函数金属层和第二金属层的第二金属栅极。 第三晶体管具有包括第三底部阻挡层，第三功函数金属层和第三金属层的第三金属栅极。 第一晶体管，第二晶体管和第三晶体管具有相同的导电类型。 第一底部阻挡层的氮浓度>第二底部阻挡层的氮浓度>第三底部阻挡层的氮浓度。

公开(公告)号：US20150357430A1

公开(公告)日：2015-12-10

申请号：US14324092

申请日：2014-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Lung-En Kuo ,  You-Di Jhang ,  Jian-Cun Ke

IPC: H01L29/51 ,  H01L29/40

CPC classification number: H01L29/6656 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在衬底上形成界面层; 在界面层上形成堆叠结构; 图案化堆叠结构以在界面层上形成栅极结构; 在界面层和栅极结构上形成衬垫; 以及去除衬套的一部分和用于形成间隔物的界面层的一部分。