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    Optical interposer
    1.
    发明授权
    Optical interposer 有权
    光插件

    公开(公告)号：US08757897B2

    公开(公告)日：2014-06-24

    申请号：US13362898

    申请日：2012-01-31

    申请人： Valentin Kosenko ,  Edward Lee McBain ,  Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Sergey Savastiouk

    发明人： Valentin Kosenko ,  Edward Lee McBain ,  Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Sergey Savastiouk

    IPC分类号： G02B6/36

    CPC分类号： G02B6/4214

    摘要： An optical interposer includes grooves (310) for optical fiber cables (104) coupled to a transducer (120). The grooves are formed by etching a cavity (410) in a substrate (130), filling the cavity with some layer (520), then etching the layer to form the grooves. The cavity has outwardly sloped sidewalls on which mirrors (144) are later formed. The groove etch is selective not to damage the sidewalls. The groove depth is uniform due to high etch selectivity of the layer, and also because of good control over the cavity etch due to the low aspect ratio of the cavity. Electrical circuitry for connection to the transducer is fabricated after the cavity filling but before the groove etch. The cavity filling leaves the wafer planar, facilitating fabrication of the electrical circuitry. Grooves can be provided on top and bottom of the interposer. Other features are also provided.

    摘要翻译： 光学插入器包括耦合到换能器（120）的光纤电缆（104）的凹槽（310）。 凹槽通过蚀刻衬底（130）中的空腔（410）形成，用一些层（520）填充空腔，然后蚀刻该层以形成凹槽。 空腔具有向外倾斜的侧壁，后面形成有反射镜（144）。 凹槽蚀刻是选择性的，不损坏侧壁。 由于该层的高蚀刻选择性，凹槽深度是均匀的，并且还由于腔的低纵横比由于对腔蚀刻的良好控制。 用于连接到换能器的电路在腔填充之后但在凹槽蚀刻之前制造。 空腔填充离开晶片平面，便于制造电路。 可以在插入器的顶部和底部提供凹槽。 还提供其他功能。

    Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques
    2.
    发明授权
    Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques 有权
    介质沟槽，镍/氧化钽结构和化学机械抛光技术

    公开(公告)号：US08633589B2

    公开(公告)日：2014-01-21

    申请号：US11866186

    申请日：2007-10-02

    申请人： Sergey Savastiouk ,  Valentin Kosenko ,  James J. Roman

    发明人： Sergey Savastiouk ,  Valentin Kosenko ,  James J. Roman

    IPC分类号： H01L23/48

    CPC分类号： H01L28/40 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5223 ,  H01L23/53238 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/3025

    摘要： A portion of a conductive layer (310, 910) provides a capacitor electrode (310.0, 910.0). Dielectric trenches (410, 414, 510) are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric (320) can be formed by anodizing tantalum while a nickel layer (314) protects an underlying copper (310) from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer (610) is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.

    摘要翻译： 导电层（310,910）的一部分提供电容器电极（310.0,910.0）。 电介质沟槽（410,414,510）形成在导电层中，以将电容器电极与用于穿过电极但与电极绝缘的导电路径的导电层的那些部分绝缘。 可以通过阳极氧化钽形成电容器电介质（320），同时镍层（314）保护底层铜（310）与阳极氧化溶液。 该保护允许使钽层变薄以获得大的电容。 通过首先对该层进行光刻图案化以形成和/或增加该层的向上突起，使层（610）的化学机械抛光更快，因此可能更便宜。

    OPTICAL INTERPOSER
    8.
    发明申请
    OPTICAL INTERPOSER 有权
    光学插件

    公开(公告)号：US20130177281A1

    公开(公告)日：2013-07-11

    申请号：US13362898

    申请日：2012-01-31

    申请人： Valentin Kosenko ,  Edward Lee McBain ,  Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Sergey Savastiouk

    发明人： Valentin Kosenko ,  Edward Lee McBain ,  Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Sergey Savastiouk

    IPC分类号： G02B6/42 ,  H01B13/00 ,  B44C1/22

    CPC分类号： G02B6/4214

    摘要： An optical interposer includes grooves (310) for optical fiber cables (104) coupled to a transducer (120). The grooves are formed by etching a cavity (410) in a substrate (130), filling the cavity with some layer (520), then etching the layer to form the grooves. The cavity has outwardly sloped sidewalls on which mirrors (144) are later formed. The groove etch is selective not to damage the sidewalls. The groove depth is uniform due to high etch selectivity of the layer, and also because of good control over the cavity etch due to the low aspect ratio of the cavity. Electrical circuitry for connection to the transducer is fabricated after the cavity filling but before the groove etch. The cavity filling leaves the wafer planar, facilitating fabrication of the electrical circuitry. Grooves can be provided on top and bottom of the interposer. Other features are also provided.

    摘要翻译： 光学插入器包括耦合到换能器（120）的光纤电缆（104）的凹槽（310）。 凹槽通过蚀刻衬底（130）中的空腔（410）形成，用一些层（520）填充空腔，然后蚀刻该层以形成凹槽。 空腔具有向外倾斜的侧壁，后面形成有反射镜（144）。 凹槽蚀刻是选择性的，不损坏侧壁。 由于该层的高蚀刻选择性，凹槽深度是均匀的，并且还由于腔的低纵横比由于对腔蚀刻的良好控制。 用于连接到换能器的电路在腔填充之后但在凹槽蚀刻之前制造。 空腔填充离开晶片平面，便于制造电路。 可以在插入器的顶部和底部提供凹槽。 还提供其他功能。

    STRUCTURES WITH THROUGH VIAS PASSING THROUGH A SUBSTRATE COMPRISING A PLANAR INSULATING LAYER BETWEEN SEMICONDUCTOR LAYERS
    10.
    发明申请
    STRUCTURES WITH THROUGH VIAS PASSING THROUGH A SUBSTRATE COMPRISING A PLANAR INSULATING LAYER BETWEEN SEMICONDUCTOR LAYERS 有权
    通过通过包含半导体层之间的平面绝缘层的基板通过VIAS的结构

    公开(公告)号：US20130015585A1

    公开(公告)日：2013-01-17

    申请号：US13181006

    申请日：2011-07-12

    申请人： Valentin Kosenko ,  Sergey Savastiouk

    发明人： Valentin Kosenko ,  Sergey Savastiouk

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L23/5384 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06541 ,  H01L2924/1461 ,  H01L2924/00

    摘要： A through via contains a conductor (244, 262) passing through a substrate (140). The substrate can be SOI or some other substrate containing two semiconductor layers (140.1, 140.2) on opposite sides of an insulating layer (140B). The through via includes two constituent vias (144.1, 144.2) formed from respective different sides of the substrate by processes stopping on the insulating layer (140B). Due to the insulating layer acting as a stop layer, high control over the constituent vias' depths is achieved. Each constituent via is shorter than the through via, so via formation is facilitated. The conductor is formed by separate depositions of conductive material into the constituent vias from each side of the substrate. From each side, the conductor is deposited to a shallower depth than the through-via depth, so the deposition is facilitated. Other embodiments are also provided.

    摘要翻译： 通孔包含穿过衬底（140）的导体（244,262）。 衬底可以是在绝缘层（140B）的相对侧上包含两个半导体层（140.1,140.2）的SOI或一些其它衬底。 通孔包括通过在绝缘层（140B）上停止的工艺从基板的各个不同侧形成的两个构成通孔（144.1,144.2）。 由于绝缘层作为停止层，实现了对组成通孔深度的高度控制。 每个组分通孔比通孔更短，因此通过形成便利。 导体由导电材料从衬底的每一侧分离成为组成通孔形成。 从每侧，导体被沉积到比通孔深度更浅的深度，因此便于沉积。 还提供了其他实施例。