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    Nonvolatile memory device having wear-leveling control and method of operating the same
    2.
    发明授权
    Nonvolatile memory device having wear-leveling control and method of operating the same 有权
    具有磨损均衡控制的非易失性存储器件及其操作方法

    公开(公告)号：US09372790B2

    公开(公告)日：2016-06-21

    申请号：US13954135

    申请日：2013-07-30

    申请人： Wonseok Lee ,  Youngkug Moon ,  Taek-Sung Kim

    发明人： Wonseok Lee ,  Youngkug Moon ,  Taek-Sung Kim

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F2212/7211

    摘要： A method is provided for controlling a write operation in a nonvolatile memory device to provide wear leveling, where the nonvolatile memory device includes multiple memory blocks. The method includes reading write indication information with respect to at least a selected memory block of the multiple memory blocks; determining whether a write order of data to be stored in the selected memory block is an ascending order or a descending order, based on the write indication information of the selected memory block; and generating addresses of memory regions in the selected memory block in an ascending order when the write order of the data is determined to be an ascending order, and generating addresses of the memory regions in the selected memory block in a descending order when the write order is determined to be a descending order.

    摘要翻译： 提供了一种用于控制非易失性存储器件中的写入操作以提供损耗均衡的方法，其中非易失性存储器件包括多个存储器块。 所述方法包括：读取至少所述多个存储块的所选存储块的写入指示信息; 基于所选择的存储块的写入指示信息，确定要存储在所选存储器块中的数据的写入顺序是升序还是降序; 以及当所述数据的写入顺序被确定为升序时，以升序生成所选择的存储器块中的存储器区域的地址，并且当所述写入顺序为低时产生所选存储器块中的存储器区域的地址 被确定为降序。

    Data storage device, controller, and operating method of data storage device
    3.
    发明授权
    Data storage device, controller, and operating method of data storage device 有权
    数据存储设备，数据存储设备的控制器和操作方法

    公开(公告)号：US09153332B2

    公开(公告)日：2015-10-06

    申请号：US14059852

    申请日：2013-10-22

    申请人： Wonseok Lee ,  Eun-Jin Yun ,  Youngkug Moon ,  Seongsik Hwang ,  Donghyun Sohn

    发明人： Wonseok Lee ,  Eun-Jin Yun ,  Youngkug Moon ,  Seongsik Hwang ,  Donghyun Sohn

    IPC分类号： G11C7/00 ,  G11C16/22 ,  G11C7/20 ,  G11C8/20 ,  G11C7/06

    CPC分类号： G11C16/22 ,  G11C7/06 ,  G11C7/20 ,  G11C8/20

    摘要： A nonvolatile memory is provided which includes a memory cell array including a plurality of nonvolatile memory cells; a decoder connected with the memory cell array through a plurality of word lines; a data input/output circuit connected with the memory cell array through a plurality of bit lines; a voltage detector configured to detect a variation in a power supply voltage to output a voltage variation signal; and control logic configured to control the decoder and the data input/output circuit such that data stored at the memory cell array is invalidated in response to the voltage variation signal.

    摘要翻译： 提供一种非易失性存储器，其包括：包括多个非易失性存储单元的存储单元阵列; 通过多个字线与存储单元阵列连接的解码器; 通过多个位线与存储单元阵列连接的数据输入/输出电路; 电压检测器，被配置为检测电源电压的变化以输出电压变化信号; 以及控制逻辑，被配置为控制解码器和数据输入/输出电路，使得存储在存储单元阵列处的数据响应于电压变化信号而无效。

    Semiconductor memory device having variable resistance memory and operating method
    5.
    发明授权
    Semiconductor memory device having variable resistance memory and operating method 有权
    具有可变电阻存储器和操作方法的半导体存储器件

    公开(公告)号：US09311981B2

    公开(公告)日：2016-04-12

    申请号：US13954161

    申请日：2013-07-30

    申请人： Wonseok Lee ,  Seonghyun Jeon ,  Youngkug Moon ,  Dong Hwi Kim

    发明人： Wonseok Lee ,  Seonghyun Jeon ,  Youngkug Moon ,  Dong Hwi Kim

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1675 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1695

    摘要： A semiconductor memory device includes a memory cell array of nonvolatile memory cells having a variable resistance element, and a conductor line array capable of generating a compensation magnetic field for the nonvolatile memory cells. A current driver selectively supplies current to conductive lines, a magnetic field sensor senses an applied external magnetic field and generates external magnetic field information, and a controller controls generation of the compensation magnetic field in response to the external magnetic field information.

    摘要翻译： 半导体存储器件包括具有可变电阻元件的非易失性存储单元的存储单元阵列和能够产生用于非易失性存储单元的补偿磁场的导线阵列。 电流驱动器选择性地向导线提供电流，磁场传感器感测施加的外部磁场并产生外部磁场信息，并且控制器响应于外部磁场信息控制补偿磁场的产生。

    DATA STORAGE SYSTEM HAVING MULTI-BIT MEMORY DEVICE AND OPERATING METHOD THEREOF
    6.
    发明申请
    DATA STORAGE SYSTEM HAVING MULTI-BIT MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
    具有多位存储器件的数据存储系统及其操作方法

    公开(公告)号：US20130141972A1

    公开(公告)日：2013-06-06

    申请号：US13737140

    申请日：2013-01-09

    申请人： Sangyong Yoon ,  Kitae Park ,  Jinman Han ,  Wonseok Lee

    发明人： Sangyong Yoon ,  Kitae Park ,  Jinman Han ,  Wonseok Lee

    IPC分类号： G11C16/10 ,  G11C16/26

    CPC分类号： G11C16/10 ,  G11C11/56 ,  G11C11/5628 ,  G11C14/0018 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

    摘要： A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory and which controls the non-volatile memory device. The operating method of the data storage device includes storing data in the buffer memory according to an external request, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the determined program pattern.

    摘要翻译： 数据存储装置包括：非易失性存储装置，其包括存储单元阵列; 以及包括缓冲存储器并且控制非易失性存储器件的存储器控​​制器。 数据存储装置的操作方法包括根据外部请求将数据存储在缓冲存储器中，并且确定存储在缓冲存储器中的数据是否是与存储单元阵列的缓冲器程序操作相关的数据。 当存储在缓冲存储器中的数据是与缓冲器程序操作相关的数据时，该方法还包括确定是否需要对存储单元阵列的主程序操作，以及当需要存储单元阵列的主程序操作时， 存储单元阵列中的主程序操作的程序模式。 该方法还包括基于所确定的程序模式向存储器单元阵列发出用于主程序操作的一组命令给多位存储器件。

    Dual bias frequency plasma reactor with feedback control of E.S.C. voltage using wafer voltage measurement at the bias supply output
    9.
    发明授权
    Dual bias frequency plasma reactor with feedback control of E.S.C. voltage using wafer voltage measurement at the bias supply output 有权
    具有E.S.C.反馈控制的双偏压等离子体反应器 电压使用晶圆电压测量在偏置电源输出

    公开(公告)号：US07359177B2

    公开(公告)日：2008-04-15

    申请号：US11127036

    申请日：2005-05-10

    申请人： Jang Gyoo Yang ,  Daniel J. Hoffman ,  Steven C. Shannon ,  Douglas H. Burns ,  Wonseok Lee ,  Kwang-Soo Kim

    发明人： Jang Gyoo Yang ,  Daniel J. Hoffman ,  Steven C. Shannon ,  Douglas H. Burns ,  Wonseok Lee ,  Kwang-Soo Kim

    IPC分类号： H01L21/683 ,  H01T23/00 ,  G01L21/30 ,  G01R31/00 ,  H01J7/24 ,  H05B31/26 ,  C23F1/00 ,  H01L21/306

    CPC分类号： H01J37/32706 ,  H01J37/32935 ,  H01L21/6833 ,  Y10T279/23

    摘要： A plasma reactor has a dual frequency plasma RF bias power supply furnishing RF bias power comprising first and second frequency components, f(1), f(2), respectively, and an RF power path having an input end coupled to the plasma RF bias power supply and an output end coupled to the wafer support pedestal, and sensor circuits providing measurement signals representing first and second frequency components of a measured voltage and first and second frequency components of a measured current near the input end of the RF power path. The reactor further includes a processor for providing first and second frequency components of a wafer voltage signal as, respectively, a first sum of the first frequency components of the measured voltage and measured current multiplied by first and second coefficients respectively, and a second sum of the second frequency components of the measured voltage and measured current multiplied by third and fourth coefficients, respectively. A processor produces a D.C. wafer voltage by combining D.C. components of the first and second frequency components of the wafer voltage with an intermodulation correction factor that is the product of the D.C. components of the first and second components of the wafer voltage raised to a selected power and multiplied by a selected coefficient.

    摘要翻译： 等离子体反应器具有双频等离子体RF偏压电源，其分别提供包括第一和第二频率分量f（1），f（2）的RF偏置功率，以及具有耦合到等离子体RF偏置的输入端的RF功率路径 电源和耦合到晶片支撑基座的输出端，以及传感器电路，其提供表示测量电压的第一和第二频率分量以及在RF功率路径的输入端附近的测量电流的第一和第二频率分量的测量信号。 反应器还包括处理器，用于分别提供晶片电压信号的第一和第二频率分量，分别为测量电压的第一频率分量和测量电流乘以第一和第二系数的第一和，以及第二和 测量电压和测量电流的第二频率分量分别乘以第三和第四系数。 处理器通过将晶片电压的第一和第二频率分量的DC分量与作为晶片电压的第一和第二分量的DC分量升高到所选功率的互调校正因子相结合来产生DC晶片电压 并乘以所选系数。

    Dielectric plasma etch process with in-situ amorphous carbon mask with improved critical dimension and etch selectivity
    10.
    发明申请
    Dielectric plasma etch process with in-situ amorphous carbon mask with improved critical dimension and etch selectivity 失效
    介质等离子体蚀刻工艺，具有改进的临界尺寸和蚀刻选择性的原位无定形碳掩模

    公开(公告)号：US20070249171A1

    公开(公告)日：2007-10-25

    申请号：US11434951

    申请日：2006-05-16

    申请人： Shing-Li Sung ,  Wonseok Lee ,  Judy Wang ,  Shawming Ma

    发明人： Shing-Li Sung ,  Wonseok Lee ,  Judy Wang ,  Shawming Ma

    IPC分类号： H01L21/461 ,  H01L21/302

    CPC分类号： H01L21/76802 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76814

    摘要： A plasma-enhanced process is performed in a single plasma reactor chamber for etching a thin film layer on a workpiece, using a hard mask layer including an amorphous carbon layer (ACL) overlying the thin film layer and an anti-reflection coating (ARC) overlying the ACL. The process includes etching a pattern in the ARC in accordance with a photoresist mask overlying the ARC, using a plasma produced from a fluorine-containing process gas, and then removing fluorine-containing residue from the reactor chamber and/or workpiece by performing a first transition step by replacing the fluorine-containing process gas with an inert species process gas and maintaining a plasma in the reactor chamber. A pattern is then etched in the ACL using the ARC as an etch mask by replacing the argon process gas with a process gas containing hydrogen while maintaining a plasma in the chamber. Thereafter, hydrogen-containing residue is removed from the reactor and/or from the chamber by performing a flush step by replacing the hydrogen-containing process gas with argon gas and maintaining a plasma in the chamber. The process continues with etching a pattern in the thin film layer using the ACL as a hard mask by replacing the argon gas in the chamber with a species capable of etching the thin film layer.

    摘要翻译： 使用包括覆盖在薄膜层上的无定形碳层（ACL）和抗反射涂层（ARC）的硬掩模层，在单个等离子体反应器室中进行等离子体增强处理，以蚀刻工件上的薄膜层， 覆盖ACL。 该方法包括使用由含氟工艺气体产生的等离子体，根据覆盖在ARC上的光致抗蚀剂掩模蚀刻ARC中的图案，然后通过执行第一步骤从反应器室和/或工件中除去含氟残留物 通过用惰性物质处理气体代替含氟工艺气体并在反应器室中维持等离子体来实现。 然后使用ARC作为蚀刻掩模在ACL中蚀刻图案，通过用含有氢气的工艺气体代替氩气工艺气体，同时保持室内的等离子体。 此后，通过用氩气代替含氢处理气体并在室内维持等离子体，通过进行冲洗步骤从反应器和/或从室除去含氢残留物。 该过程继续以使用ACL作为硬掩模在薄膜层中蚀刻图案，通过用能够蚀刻薄膜层的种类替换室内的氩气。