公开(公告)号：US5287000A

公开(公告)日：1994-02-15

申请号：US674969

申请日：1991-03-26

申请人： Yasushi Takahashi ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai ,  Masaya Muranaka ,  Yoshitaka Kinoshita ,  Satoru Koshiba

发明人： Yasushi Takahashi ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai ,  Masaya Muranaka ,  Yoshitaka Kinoshita ,  Satoru Koshiba

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L27/10 ,  H01L29/44 ,  H02G3/08

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/49541 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2224/49171 ,  H01L2224/49179 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011

摘要： According to one aspect of the present invention, a semiconductor chip, which can be mounted in a zigzag in-line type package (ZIP) partially using a tabless lead frame, includes bonding pads arranged on the chip so that the chip can be applied also to other different types of packages. These different types of packages include a small out-line J-bent type package (SOJ) which uses a lead frame with tab, and a dual in-line type package (DIP) which uses a tabless lead frame. Further, a plurality of bonding pad pairs are provided amongst the bonding pads on the chip, each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to make the semiconductor chip compatible with a variety of or different types of packages. In accordance with another aspect of the invention, a resin-encapsulated semiconductor device of the ZIP structure is provided in which a semiconductor pellet having a plurality of external terminals disposed on a device-forming surface along each side of the planar shape is encapsulated with a resin, wherein inner leads for signals connected electrically with external terminals, disposed opposing to the surface of the resin-encapsulated portion disposed with outer leads and disposed along the most remote side of the semiconductor pellet, are arranged so as to overlap the semiconductor pellet.

摘要翻译： 根据本发明的一个方面，可以使用无引线引线框架部分地以锯齿形的在线型封装（ZIP）安装的半导体芯片包括布置在芯片上的焊盘，使得芯片也可以被应用 到其他不同类型的包。 这些不同类型的封装包括使用带引脚的引线框架的小型外部J型弯曲型封装（SOJ）和使用无引脚引线框架的双列直插型封装（DIP）。 此外，在芯片上的接合焊盘之间设置多个接合焊盘对，这种接合焊盘对的每个焊盘具有与其相关联的另一个焊盘相同的功能，从而在半导体芯片上的不同接合焊盘中复制共同的功能，以便 使半导体芯片与各种或不同类型的封装兼容。 根据本发明的另一方面，提供了一种ZIP结构的树脂封装的半导体器件，其中具有设置在沿着平面形状的每一侧的器件形成表面上的多个外部端子的半导体芯片被封装在 树脂，其中与外部端子电连接的信号的内部引线设置成与设置有外部引线并沿着半导体芯片的最远侧设置的树脂封装部分的表面相对设置，以与半导体芯片重叠。

公开(公告)号：US5426613A

公开(公告)日：1995-06-20

申请号：US972907

申请日：1992-11-06

申请人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

发明人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C29/027 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1045 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/78

摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

摘要翻译： 提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。 结合这些，接合垫被布置在适于不同包装类型的最佳位置处。 还提供了各种布局布置以最小化空间并改善访问时间。 提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

公开(公告)号：US4934820A

公开(公告)日：1990-06-19

申请号：US256862

申请日：1988-10-12

申请人： Yasushi Takahashi ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai ,  Masaya Muranaka

发明人： Yasushi Takahashi ,  Kazuyuki Miyazawa ,  Hidetoshi Iwai ,  Masaya Muranaka

IPC分类号： H01L21/60 ,  G11C11/401 ,  H01L23/495 ,  H01L23/50

CPC分类号： H01L24/49 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49555 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011

摘要： According to the present invention, a semiconductor chip is mounted on a zigzag in-line type package (ZIP) partially using a tabless lead frame and bonding pads are arranged on the chip so that the chip can be applied also to other different types of packages. As different types of packages there are a small out-line J-bent type package (SOJ) for which there is used a lead frame with tab and a dual in-line type package (DIP) for which there is used a tabless lead frame. Further, a plurality of bonding pad pairs are provided among the bonding pads on the chip each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to readily facilitate, or make compatible, the semiconductor chip to a variety of or different types of packages.

摘要翻译： 根据本发明，半导体芯片部分地使用无引线引线框安装在Z字形在线型封装（ZIP）上，并且焊盘布置在芯片上，使得芯片也可以应用于其他不同类型的封装 。 作为不同类型的封装，有一个小型的外部J型弯曲型封装（SOJ），其中使用了带有引脚的引线框架和双列直插式封装（DIP），其中使用无引脚引线框架 。 此外，在芯片上的接合焊盘之间设置多个接合焊盘对，这样的焊盘对的每个焊盘具有与其相关的另一焊盘相同的功能，从而在半导体芯片上的不同接合焊盘中复制共同的功能，以便 容易地将半导体芯片促进或兼容到各种或不同类型的封装。

公开(公告)号：US5217917A

公开(公告)日：1993-06-08

申请号：US496280

申请日：1990-03-20

申请人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takemuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

发明人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takemuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50

CPC分类号： G11C29/027 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1045 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/78

摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

摘要翻译： 提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。 结合这些，接合垫被布置在适于不同包装类型的最佳位置处。 还提供了各种布局布置以最小化空间并改善访问时间。 提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

公开(公告)号：US5151772A

公开(公告)日：1992-09-29

申请号：US616705

申请日：1990-11-20

申请人： Yasushi Takahashi ,  Hiromi Matsuura ,  Yoshihisa Koyama ,  Masaya Muranaka ,  Katsutaka Kimura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Hidetoshi Iwai

发明人： Yasushi Takahashi ,  Hiromi Matsuura ,  Yoshihisa Koyama ,  Masaya Muranaka ,  Katsutaka Kimura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Hidetoshi Iwai

IPC分类号： H01L23/522 ,  H01L27/108

CPC分类号： H01L23/5226 ,  H01L27/10805 ,  H01L2924/0002 ,  Y10S257/923

摘要： A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.

摘要翻译： 提供一种半导体集成电路器件，其包括位于半导体衬底的大致中心区域中的存储单元阵列，其具有位于半导体衬底两端的外围电路。 还提供了将外围电路彼此耦合的布线层。 该布线层被布置成具有彼此电耦合的第一和第二铝层的双层结构。

公开(公告)号：US5805513A

公开(公告)日：1998-09-08

申请号：US432867

申请日：1995-05-02

申请人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

发明人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/027 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1045 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/78

摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

公开(公告)号：US5208782A

公开(公告)日：1993-05-04

申请号：US892708

申请日：1992-05-29

申请人： Toshiyuki Sakuta ,  Masamichi Ishihara ,  Kazuyuki Miyazawa ,  Masanori Tazunoki ,  Hidetoshi Iwai ,  Hisashi Nakamura ,  Yasushi Takahashi ,  Toshio Maeda ,  Hiromi Matsuura ,  Ryoichi Hori ,  Toshio Sasaki ,  Osamu Sakai ,  Hiroyuki Uchiyama ,  Eiji Miyamoto ,  Kazuyoshi Oshima ,  Yasuhiro Kasama

发明人： Toshiyuki Sakuta ,  Masamichi Ishihara ,  Kazuyuki Miyazawa ,  Masanori Tazunoki ,  Hidetoshi Iwai ,  Hisashi Nakamura ,  Yasushi Takahashi ,  Toshio Maeda ,  Hiromi Matsuura ,  Ryoichi Hori ,  Toshio Sasaki ,  Osamu Sakai ,  Hiroyuki Uchiyama ,  Eiji Miyamoto ,  Kazuyoshi Oshima ,  Yasuhiro Kasama

IPC分类号： G06F11/18 ,  G06F11/20 ,  G11C11/406 ,  G11C29/00 ,  H01L27/105 ,  H01L27/108

CPC分类号： G11C29/808 ,  G11C11/406 ,  G11C29/88 ,  H01L24/06 ,  H01L27/10805 ,  G06F11/1666 ,  G06F11/183 ,  H01L2224/4826 ,  H01L27/105 ,  H01L2924/13091 ,  H01L2924/14

摘要： A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.

摘要翻译： 提供了一种半导体集成电路存储器结构，其使用宏单元电路块，其可以在单个芯片上允许非常大的存储能力（例如，DRAM中的64Mbits）。 为了实现这一点，可以提供多个宏单元存储器块，其中每个存储器块包括存储器阵列以及诸如地址选择电路和输入/输出电路的附加电路。 在芯片上提供了多个宏单元存储块通用的其他外围电路。 宏单元存储器块本身可以形成为阵列，使得它们的组合存储容量将形成芯片的大的总体存储容量。 宏单元存储器块和用于控制存储器块的公共外围电路的组合允许DRAM的更快更有效的刷新操作。 这通过与存储器块结合使用的LOC（片上芯片）布置来增强。

公开(公告)号：US06426560B1

公开(公告)日：2002-07-30

申请号：US09608149

申请日：2000-06-30

申请人： Masayasu Kawamura ,  Atsushi Nakamura ,  Yoshihiro Sakaguchi ,  Yoshitaka Kinoshita ,  Yasushi Takahashi ,  Yoshihiko Inoue

发明人： Masayasu Kawamura ,  Atsushi Nakamura ,  Yoshihiro Sakaguchi ,  Yoshitaka Kinoshita ,  Yasushi Takahashi ,  Yoshihiko Inoue

IPC分类号： H01L27108

CPC分类号： H01L23/49537 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12 ,  H01L23/4951 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： Two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units. A memory module is so constructed that a plurality of such semiconductor storage devices, in each of which two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units, are mounted on a mounting circuit board which is square and which is formed with electrodes along one latus thereof.

摘要翻译： 以2位为单位进行存储器访问的两个存储器芯片通过将它们的背面放置在另一个上而被组装成堆叠结构，以便以4位单元进行存储器访问。 存储器模块被构造成使得多个这样的半导体存储器件，其中每个存储器芯片每个以2位单元进行存储器访问，通过将它们的背面放置在另一个上而被组装成堆叠结构，因此 为了以4位单位进行存储器访问，安装在正方形的安装电路板上，并且沿其一个区域形成有电极。

公开(公告)号：US06566760B1

公开(公告)日：2003-05-20

申请号：US09666063

申请日：2000-09-19

申请人： Masayasu Kawamura ,  Atsushi Nakamura ,  Yoshihiro Sakaguchi ,  Yoshitaka Kinoshita ,  Yasushi Takahashi ,  Yoshihiko Inoue

发明人： Masayasu Kawamura ,  Atsushi Nakamura ,  Yoshihiro Sakaguchi ,  Yoshitaka Kinoshita ,  Yasushi Takahashi ,  Yoshihiko Inoue

IPC分类号： H01L2302

CPC分类号： H01L23/49537 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12 ,  H01L23/4951 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： Two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units. A memory module is so constructed that a plurality of such semiconductor storage devices, in each of which two memory chips each being subjected to memory accesses in 2-bit units are assembled into a stacked structure by placing their back surfaces one over the other, so as to make memory accesses in 4-bit units, are mounted on a mounting circuit board which is square and which is formed with electrodes along one latus thereof.

公开(公告)号：US08068379B1

公开(公告)日：2011-11-29

申请号：US09050946

申请日：1998-03-31

申请人： Tsutomu Takahashi ,  Kouji Arai ,  Yasushi Takahashi ,  Atsuya Tanaka ,  Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira

发明人： Tsutomu Takahashi ,  Kouji Arai ,  Yasushi Takahashi ,  Atsuya Tanaka ,  Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira

IPC分类号： G11C8/00

CPC分类号： H01L27/0207 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4097 ,  H01L27/10891

摘要： A plurality of sub word lines each have a length equivalent to the division of a main word line along the extension direction thereof, arranged along a bit line crossing said main word line, and are connected with a plurality of memory cells. A first sub word select line arranged in parallel to the main word line is extended to a plurality of sub arrays arranged in the extension direction of the word line. A second sub word select line is connected to the corresponding one of said first sub word select line to be extended orthogonally to a word line driving circuit area of an adjacent sub array. In the sub word line driving circuit provided for each sub array, a sub word line is selected and deselected by signals supplied from said main word line and said second sub word select line.

摘要翻译： 多个子字线各自具有与沿着其延伸方向的主字线的划分相等的长度，沿着与所述主字线交叉的位线布置，并且与多个存储单元连接。 与主字线平行布置的第一子字选择线被扩展到沿字线的延伸方向布置的多个子阵列。 第二子字选择线连接到所述第一子字选择线中的相应一个，以与正交相邻子阵列的字线驱动电路区域正交延伸。 在为每个子阵列提供的子字线驱动电路中，通过从所述主字线和所述第二子字选择线提供的信号来选择和取消副字线。