公开(公告)号：US08487317B2

公开(公告)日：2013-07-16

申请号：US12382955

申请日：2009-03-27

申请人： Yi-Chieh Lin ,  Cheng-Ta Kuo ,  Yu-Pin Hsu ,  Chi-Ming Tsai

发明人： Yi-Chieh Lin ,  Cheng-Ta Kuo ,  Yu-Pin Hsu ,  Chi-Ming Tsai

IPC分类号： H01L33/00 ,  H01L29/20

CPC分类号： H01L33/12 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02642 ,  H01L21/02647 ,  H01L33/007

摘要： This invention discloses a GaN semiconductor device comprising a substrate; a metal-rich nitride compound thin film on the substrate; a buffer layer formed on the metal-rich nitride compound thin film, and a semiconductor stack layer on the buffer layer wherein the metal-dominated nitride compound thin film covers a partial upper surface of the substrate. Because metal-rich nitride compound is amorphous, the epitaxial growth direction of the buffer layer grows upwards in the beginning and then turns laterally, and the epitaxy defects of the buffer layer also bend with the epitaxial growth direction of the buffer layer. Therefore, the probability of the epitaxial defects extending to the semiconductor stack layer is reduced and the reliability of the GaN semiconductor device is improved.

公开(公告)号：US20090256159A1

公开(公告)日：2009-10-15

申请号：US12382955

申请日：2009-03-27

申请人： Yi-Chieh Lin ,  Cheng-Ta Kuo ,  Yu-Pin Hsu ,  Chi-Ming Tsai

发明人： Yi-Chieh Lin ,  Cheng-Ta Kuo ,  Yu-Pin Hsu ,  Chi-Ming Tsai

IPC分类号： H01L33/00 ,  H01L29/20

CPC分类号： H01L33/12 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02642 ,  H01L21/02647 ,  H01L33/007

摘要： This invention discloses a GaN semiconductor device comprising a substrate; a metal-rich nitride compound thin film on the substrate; a buffer layer formed on the metal-rich nitride compound thin film, and a semiconductor stack layer on the buffer layer wherein the metal-dominated nitride compound thin film covers a partial upper surface of the substrate. Because metal-rich nitride compound is amorphous, the epitaxial growth direction of the buffer layer grows upwards in the beginning and then turns laterally, and the epitaxy defects of the buffer layer also bend with the epitaxial growth direction of the buffer layer. Therefore, the probability of the epitaxial defects extending to the semiconductor stack layer is reduced and the reliability of the GaN semiconductor device is improved.

摘要翻译： 本发明公开了一种包括基板的GaN半导体器件; 在基板上形成富金属的氮化物化合物薄膜; 形成在富金属氮化物化合物薄膜上的缓冲层，以及缓冲层上的半导体堆叠层，其中金属主导的氮化物化合物薄膜覆盖基板的部分上表面。 因为富金属的氮化物是非晶体，所以缓冲层的外延生长方向在开始时向上生长然后横向变化，并且缓冲层的外延缺陷也随着缓冲层的外延生长方向而弯曲。 因此，延伸到半导体堆叠层的外延缺陷的概率降低，并且提高了GaN半导体器件的可靠性。

公开(公告)号：US08729525B2

公开(公告)日：2014-05-20

申请号：US12547073

申请日：2009-08-25

申请人： Jui-Yi Chu ,  Cheng-Ta Kuo ,  Yu-Pin Hsu ,  Chun-Kai Wang ,  Hsin-Hsien Wu ,  Yi-Chieh Lin

发明人： Jui-Yi Chu ,  Cheng-Ta Kuo ,  Yu-Pin Hsu ,  Chun-Kai Wang ,  Hsin-Hsien Wu ,  Yi-Chieh Lin

IPC分类号： H01L29/06 ,  H01L33/06

CPC分类号： H01L33/06 ,  H01L33/325

摘要： The present application relates to an opto-electronic device. The opto-electronic device includes an n-cladding layer, a p-cladding layer and a multi-quantum well structure. The multi-quantum well structure is located between the p-cladding layer and the n-cladding layer, and includes a plurality of barrier layers, a plurality of well layers and a barrier tuning layer. The barrier tuning layer is made by doping the barrier layer adjacent to the p-cladding layer with an impurity therein for changing an energy barrier thereof to improve the light extraction efficiency of the opto-electronic device.

摘要翻译： 本申请涉及一种光电器件。 光电器件包括n包层，p包层和多量子阱结构。 多量子阱结构位于p包覆层和n包层之间，并且包括多个势垒层，多个阱层和势垒调整层。 阻挡层调整层是通过将与p型包层相邻的势垒层与其中的杂质掺杂以改变其能量势垒而制成的，以提高光电器件的光提取效率。

公开(公告)号：US20100046205A1

公开(公告)日：2010-02-25

申请号：US12547073

申请日：2009-08-25

申请人： Jui-Yi CHU ,  Cheng-Ta Kuo ,  Yu-Pin Hsu ,  Chun-Kai Wang ,  Hsin-Hsien Wu ,  Yi-Chieh Lin

发明人： Jui-Yi CHU ,  Cheng-Ta Kuo ,  Yu-Pin Hsu ,  Chun-Kai Wang ,  Hsin-Hsien Wu ,  Yi-Chieh Lin

IPC分类号： G02F1/13357 ,  H01L29/15

CPC分类号： H01L33/06 ,  H01L33/325

摘要： The present application relates to an opto-electronic device. The opto-electronic device includes an n-cladding layer, a p-cladding layer and a multi-quantum well structure. The multi-quantum well structure is located between the p-cladding layer and the n-cladding layer, and includes a plurality of barrier layers, a plurality of well layers and a barrier tuning layer. The barrier tuning layer is made by doping the barrier layer adjacent to the p-cladding layer with an impurity therein for changing an energy barrier thereof to improve the light extraction efficiency of the opto-electronic device.

摘要翻译： 本申请涉及一种光电器件。 光电器件包括n包层，p包层和多量子阱结构。 多量子阱结构位于p包覆层和n包层之间，并且包括多个势垒层，多个阱层和势垒调整层。 阻挡层调整层是通过将与p型包层相邻的势垒层与其中的杂质掺杂以改变其能量势垒而制成的，以提高光电器件的光提取效率。

公开(公告)号：US07902562B2

公开(公告)日：2011-03-08

申请号：US12222814

申请日：2008-08-18

申请人： Cheng-Ta Kuo ,  Yu-Pin Hsu ,  Chun-Kai Wang ,  Jui-Yi Chu ,  Tsung-Kuang Chen

发明人： Cheng-Ta Kuo ,  Yu-Pin Hsu ,  Chun-Kai Wang ,  Jui-Yi Chu ,  Tsung-Kuang Chen

IPC分类号： H01L33/32

CPC分类号： H01L33/14

摘要： A light-emitting diode device (LED) device and manufacturing methods thereof are provided, wherein the LED device comprises a substrate, a first n-type semiconductor layer, an n-type three-dimensional electron cloud structure, a second n-type semiconductor layer, an active layer and a p-type semiconductor layer. The first n-type semiconductor layer, the n-type three-dimensional electron cloud structure, the second n-type semiconductor layer, the active layer and the p-type semiconductor layer are subsequently grown on the substrate.

摘要翻译： 提供了一种发光二极管器件（LED）器件及其制造方法，其中LED器件包括衬底，第一n型半导体层，n型三维电子云结构，第二n型半导体 层，有源层和p型半导体层。 随后，在基板上生长第一n型半导体层，n型三维电子云结构，第二n型半导体层，有源层和p型半导体层。

公开(公告)号：US20090057696A1

公开(公告)日：2009-03-05

申请号：US12222814

申请日：2008-08-18

申请人： Cheng-Ta Kuo ,  Yu-Pin Hsu ,  Chun-Kai Wang ,  Jui-Yi Chu ,  Tsung-Kuang Chen

发明人： Cheng-Ta Kuo ,  Yu-Pin Hsu ,  Chun-Kai Wang ,  Jui-Yi Chu ,  Tsung-Kuang Chen

IPC分类号： H01L33/00

CPC分类号： H01L33/14

摘要： A light-emitting diode device (LED) device and manufacturing methods thereof are provided, wherein the LED device comprises a substrate, a first n-type semiconductor layer, an n-type three-dimensional electron cloud structure, a second n-type semiconductor layer, an active layer and a p-type semiconductor layer. The first n-type semiconductor layer, the n-type three-dimensional electron cloud structure, the second n-type semiconductor layer, the active layer and the p-type semiconductor layer are subsequently grown on the substrate.

摘要翻译： 提供了一种发光二极管器件（LED）器件及其制造方法，其中LED器件包括衬底，第一n型半导体层，n型三维电子云结构，第二n型半导体 层，有源层和p型半导体层。 随后，在基板上生长第一n型半导体层，n型三维电子云结构，第二n型半导体层，有源层和p型半导体层。

公开(公告)号：US20060094138A1

公开(公告)日：2006-05-04

申请号：US11030790

申请日：2005-01-07

申请人： Wei-Chih Lai ,  Jinn-Kong Sheu ,  Chi-Ming Tsai ,  Cheng-Ta Kuo

发明人： Wei-Chih Lai ,  Jinn-Kong Sheu ,  Chi-Ming Tsai ,  Cheng-Ta Kuo

IPC分类号： H01L21/00

CPC分类号： H01L33/007 ,  H01L33/02 ,  H01L33/14 ,  H01L33/20

摘要： A method for manufacturing a high efficiency light-emitting diode (LED) is disclosed. In the method, a substrate is provided, in which an N-type buffer layer, an N-type cladding layer and an active layer are stacked on the substrate in sequence. A first P-type cladding layer is formed on the active layer. Next, a growth-interruption step is performed, and a catalyst is introduced to form a plurality of nuclei sites on a surface of the first P-type cladding layer. A second P-type cladding layer is formed on the first P-type cladding layer according to the nuclei sites, so that the second P-type cladding layer has a surface with a plurality of mesa hillocks. Then, a contact layer is formed on the second P-type cladding layer. Subsequently, a transparent electrode is formed on the contact layer.

公开(公告)号：US07153713B2

公开(公告)日：2006-12-26

申请号：US11030790

申请日：2005-01-07

申请人： Wei-Chih Lai ,  Jinn-Kong Sheu ,  Chi-Ming Tsai ,  Cheng-Ta Kuo

发明人： Wei-Chih Lai ,  Jinn-Kong Sheu ,  Chi-Ming Tsai ,  Cheng-Ta Kuo

IPC分类号： H01L21/00

CPC分类号： H01L33/007 ,  H01L33/02 ,  H01L33/14 ,  H01L33/20

摘要： A method for manufacturing a high efficiency light-emitting diode (LED) is disclosed. In the method, a substrate is provided, in which an N-type buffer layer, an N-type cladding layer and an active layer are stacked on the substrate in sequence. A first P-type cladding layer is formed on the active layer. Next, a growth-interruption step is performed, and a catalyst is introduced to form a plurality of nuclei sites on a surface of the first P-type cladding layer. A second P-type cladding layer is formed on the first P-type cladding layer according to the nuclei sites, so that the second P-type cladding layer has a surface with a plurality of mesa hillocks. Then, a contact layer is formed on the second P-type cladding layer. Subsequently, a transparent electrode is formed on the contact layer.

摘要翻译： 公开了一种用于制造高效率发光二极管（LED）的方法。 在该方法中，提供了基板，其中N型缓冲层，N型覆层和有源层依次层叠在基板上。 在有源层上形成第一P型覆层。 接下来，进行生长中断步骤，并且引入催化剂以在第一P型包覆层的表面上形成多个核部位。 根据核部位在第一P型包层上形成第二P型包覆层，使得第二P型包覆层具有多个台面小丘的表面。 然后，在第二P型包覆层上形成接触层。 随后，在接触层上形成透明电极。

公开(公告)号：US08278681B2

公开(公告)日：2012-10-02

申请号：US12469669

申请日：2009-05-20

申请人： Chia-En Lee ,  Cheng-Ta Kuo ,  Der-Ling Hsia

发明人： Chia-En Lee ,  Cheng-Ta Kuo ,  Der-Ling Hsia

IPC分类号： H01L33/00

CPC分类号： H01L33/0079 ,  H01L24/26 ,  H01L24/93 ,  H01L33/486 ,  H01L33/62 ,  H01L33/642 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/00

摘要： A wafer-level packaging process of a light-emitting diode is provided. First, a semiconductor stacked layer is formed on a growth substrate. A plurality of barrier patterns and a plurality of reflective layers are then formed on the semiconductor stacked layer, wherein each reflective layer is surrounded by one of the barrier patterns. A first bonding layer is then formed on the semiconductor stacked layer to cover the barrier patterns and the reflective layers. Thereafter, a carrying substrate having a plurality of second bonding layers and a plurality of conductive plugs electrically insulated from each other is provided, and the first bonding layer is bonded with the second bonding layer. The semiconductor stacked layer is then separated from the growth substrate. Next, the semiconductor stacked layer is patterned to form a plurality of semiconductor stacked patterns. Next, each semiconductor stacked pattern is electrically connected to the conductive plug.

摘要翻译： 提供了发光二极管的晶片级封装工艺。 首先，在生长基板上形成半导体堆叠层。 然后在半导体堆叠层上形成多个阻挡图案和多个反射层，其中每个反射层被一个屏障图案包围。 然后在半导体堆叠层上形成第一结合层以覆盖阻挡图案和反射层。 此后，设置具有多个第二接合层和彼此电绝缘的多个导电插塞的承载基板，并且第一接合层与第二接合层接合。 然后将半导体堆叠层与生长衬底分离。 接下来，对半导体堆叠层进行图案化以形成多个半导体堆叠图案。 接下来，每个半导体堆叠图案电连接到导电插头。

公开(公告)号：US20120164768A1

公开(公告)日：2012-06-28

申请号：US13403714

申请日：2012-02-23

申请人： Chia-En Lee ,  Cheng-Ta Kuo ,  Der-Ling Hsia

发明人： Chia-En Lee ,  Cheng-Ta Kuo ,  Der-Ling Hsia

IPC分类号： H01L33/60

CPC分类号： H01L33/0079 ,  H01L24/26 ,  H01L24/93 ,  H01L33/486 ,  H01L33/62 ,  H01L33/642 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/00

摘要： A wafer-level packaging process of a light-emitting diode is provided. First, a semiconductor stacked layer is formed on a growth substrate. A plurality of barrier patterns and a plurality of reflective layers are then formed on the semiconductor stacked layer, wherein each reflective layer is surrounded by one of the barrier patterns. A first bonding layer is then formed on the semiconductor stacked layer to cover the barrier patterns and the reflective layers. Thereafter, a carrying substrate having a plurality of second bonding layers and a plurality of conductive plugs electrically insulated from each other is provided, and the first bonding layer is bonded with the second bonding layer. The semiconductor stacked layer is then separated from the growth substrate. Next, the semiconductor stacked layer is patterned to form a plurality of semiconductor stacked patterns. Next, each semiconductor stacked pattern is electrically connected to the conductive plug.

摘要翻译： 提供了发光二极管的晶片级封装工艺。 首先，在生长基板上形成半导体堆叠层。 然后在半导体堆叠层上形成多个阻挡图案和多个反射层，其中每个反射层被一个屏障图案包围。 然后在半导体堆叠层上形成第一结合层以覆盖阻挡图案和反射层。 此后，设置具有多个第二接合层和彼此电绝缘的多个导电插塞的承载基板，并且第一接合层与第二接合层接合。 然后将半导体堆叠层与生长衬底分离。 接下来，对半导体堆叠层进行图案化以形成多个半导体堆叠图案。 接下来，每个半导体堆叠图案电连接到导电插头。