公开(公告)号：US20110063066A1

公开(公告)日：2011-03-17

申请号：US12642060

申请日：2009-12-18

申请人： Yong Seok CHOI ,  Yun Hwi Park ,  Won Chul Ma ,  Kuk Hyun Kim ,  Kwang Jin Ha

发明人： Yong Seok CHOI ,  Yun Hwi Park ,  Won Chul Ma ,  Kuk Hyun Kim ,  Kwang Jin Ha

IPC分类号： H01F27/28 ,  H01F41/04

CPC分类号： H01F27/2804 ,  H01F41/042 ,  H01F2027/2809 ,  Y10T29/4902

摘要： A space transformer for a probe card includes: a multilayered circuit board having first and second faces which face each other and a plurality of side faces connecting the first and second faces; a plurality of channels including a first pad formed on the first face and receiving an electrical signal applied from the exterior, a second pad formed on the second face, to which a probe is connected, and a through wiring penetrating the multilayered circuit board and connecting the first and second pads; and side wirings formed on the side faces and connecting first and second pads of a damaged channel among a plurality of channels. When a portion of channels transferring an electrical signal to probes is damaged, the space transformer can repair the damaged channel by means of the side wirings.

摘要翻译： 一种用于探针卡的空间变压器包括：具有彼此面对的第一和第二面以及连接第一和第二面的多个侧面的多层电路板; 多个通道，包括形成在第一面上并且接收从外部施加的电信号的第一焊盘，形成在第二面上的第二焊盘，探针连接到该多个通道，以及贯穿多层电路板的通孔和连接 第一和第二垫; 以及在多个通道中形成在侧面上并连接损坏通道的第一和第二焊盘的侧布线。 当传输电信号到探头的通道的一部分被损坏时，空间变压器可以通过侧面布线修复损坏的通道。

公开(公告)号：US20080303120A1

公开(公告)日：2008-12-11

申请号：US12155867

申请日：2008-06-11

申请人： Tae Soo Lee ,  Yun Hwi Park

发明人： Tae Soo Lee ,  Yun Hwi Park

IPC分类号： H01L23/552

CPC分类号： H01L23/552 ,  H01L23/13 ,  H01L23/15 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor chip package includes a main board; a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and a conductive shielding layer provided with a predetermined thickness on the outside of the ceramic substrate. The ceramic substrate includes: at least one first ground line electrically connecting the conductive shielding layer with the main board; at least one second ground line electrically connecting the conductive shielding layer with the chip; and at least one signal line electrically connecting the chip with the main board. Thus, manufacturing costs are lowered because of the reduced number of components being used, miniaturization in device design can be achieved because of the small volume of the package, and the ground performance can be improved.

摘要翻译： 半导体芯片封装包括主板; 陶瓷基板，其具有至少一个芯片电气安装的空腔，所述空腔设置在所述陶瓷基板的面对所述主板的下部; 以及在陶瓷基板的外侧设置有规定厚度的导电性屏蔽层。 陶瓷基板包括：将导电屏蔽层与主板电连接的至少一个第一接地线; 将所述导电屏蔽层与所述芯片电连接的至少一个第二接地线; 以及将芯片与主板电连接的至少一个信号线。 因此，由于使用的部件数量减少，制造成本降低，因为可以实现小型化的装置设计，因为包装体积小，并且可以提高地面性能。

公开(公告)号：US20130032384A1

公开(公告)日：2013-02-07

申请号：US13565249

申请日：2012-08-02

申请人： Won Hee Yoo ,  Byeung Gyu Chang ,  Taek Jung Lee ,  Yun Hwi Park

发明人： Won Hee Yoo ,  Byeung Gyu Chang ,  Taek Jung Lee ,  Yun Hwi Park

IPC分类号： H05K1/03 ,  H05K3/22

CPC分类号： H05K3/243 ,  H05K1/0306 ,  H05K3/107 ,  H05K3/108 ,  H05K2201/0338

摘要： Disclosed herein are a thin film electrode ceramic substrate and a method for manufacturing the same. The thin film electrode ceramic substrate includes: a ceramic substrate; a thin film electrode pattern formed on the ceramic substrate; and a plating layer formed on the thin film electrode pattern, wherein the plating layer is formed above the thin film electrode pattern and on both lateral surfaces of the thin film electrode pattern. According to the present invention, an undercut defect occurring between the surface of the ceramic substrate and the thin film electrode pattern and between the thin film electrode patterns due to an etchant can be prevented, by forming a plating layer above the thin film electrode pattern or on both lateral surfaces of the thin film electrode pattern, or forming an intaglio type anti-etching metal layer in the surface of the ceramic substrate.

摘要翻译： 本文公开了一种薄膜电极陶瓷基板及其制造方法。 薄膜电极陶瓷基板包括：陶瓷基板; 形成在陶瓷基板上的薄膜电极图案; 以及形成在所述薄膜电极图案上的镀层，其中所述镀层形成在所述薄膜电极图案的上方以及所述薄膜电极图案的两个侧面上。 根据本发明，通过在薄膜电极图案上方形成镀层，可以防止在陶瓷基板的表面与薄膜电极图案之间以及由于蚀刻剂引起的薄膜电极图案之间发生的底切缺陷，或 在薄膜电极图案的两个侧表面上，或在陶瓷基板的表面中形成凹版型的抗蚀刻金属层。

公开(公告)号：US20080238553A1

公开(公告)日：2008-10-02

申请号：US12049005

申请日：2008-03-14

申请人： Yun Hee CHO ,  Chul Soon Park ,  Ji Hoon Kim ,  Yun Hwi Park

发明人： Yun Hee CHO ,  Chul Soon Park ,  Ji Hoon Kim ,  Yun Hwi Park

IPC分类号： H03F3/04

CPC分类号： H03F1/0266 ,  H03F1/32 ,  H03F2200/18

摘要： There is provided a power amplifying device having a linearizer in which a bias circuit has an initial impedance set when initially operated, then the impedance is varied according to a level of an input signal and the input signal is amplified in a broad range from a low level region to a high level region, thereby improving linearity of an output signal. The power amplifying device including: an amplifying unit receiving a bias power source and amplifying an input signal; a bias unit varying the bias power source according to a set impedance to provide to the amplifying unit; and an impedance setting unit setting the impedance of the bias unit in response to a preset control voltage when the bias unit is initially operated and re-setting the impedance of the bias unit according to a level of the input signal of the amplifying unit after initial operation of the bias unit.

摘要翻译： 提供一种功率放大装置，其具有线性化装置，其中偏置电路在初始操作时具有设定的初始阻抗，然后根据输入信号的电平来改变阻抗，并且输入信号在低范围内被放大 电平区域到高电平区域，从而提高输出信号的线性度。 功率放大装置包括：放大单元，接收偏置电源并放大输入信号; 偏置单元根据设定的阻抗改变偏置电源以提供给放大单元; 以及阻抗设定单元，当偏置单元初始操作时，响应于预设的控制电压来设定偏置单元的阻抗，并根据放大单元的输入信号的电平在初始化之后重新设置偏置单元的阻抗 偏置单元的操作。

公开(公告)号：US20100102430A1

公开(公告)日：2010-04-29

申请号：US12476221

申请日：2009-06-01

申请人： Tae Soo LEE ,  Yun Hwi Park ,  Yun Hee Cho

发明人： Tae Soo LEE ,  Yun Hwi Park ,  Yun Hee Cho

IPC分类号： H01L23/488 ,  H01L23/48

CPC分类号： H01L25/16 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor multichip package includes a substrate having a top surface on which a bonding pad is formed, and a bottom surface opposing the top surface, on which an external connection terminal electrically connected with the bonding pad is formed, a first semiconductor chip mounted on a region of the top surface of the substrate excluding the bonding pad, a ceramic spacer disposed on a top surface of the first semiconductor chip and including a passive device therein, and at least one second semiconductor chip disposed on a top surface of the ceramic spacer. The ceramic spacer includes an interlayer circuit for an electrical connection between the first and second semiconductor chips, and the passive device is electrically connected to at least one of the first and second semiconductor chips. Accordingly, a package with a more compact structure can be realized.

摘要翻译： 一种半导体多芯片封装，包括具有形成有焊盘的顶面的基板和与形成有与焊盘电连接的外部连接端子的上表面的底面，安装在焊盘上的第一半导体芯片 除了焊盘之外的衬底的顶表面的区域，设置在第一半导体芯片的顶表面上并且包括其中的无源器件的陶瓷间隔件和设置在陶瓷间隔件的顶表面上的至少一个第二半导体芯片。 陶瓷间隔件包括用于第一和第二半导体芯片之间的电连接的层间电路，并且无源器件电连接到第一和第二半导体芯片中的至少一个。 因此，可以实现具有更紧凑结构的封装。

公开(公告)号：US07692490B2

公开(公告)日：2010-04-06

申请号：US12049005

申请日：2008-03-14

申请人： Yun Hee Cho ,  Chul Soon Park ,  Ji Hoon Kim ,  Yun Hwi Park

发明人： Yun Hee Cho ,  Chul Soon Park ,  Ji Hoon Kim ,  Yun Hwi Park

IPC分类号： H03F3/04

CPC分类号： H03F1/0266 ,  H03F1/32 ,  H03F2200/18

摘要： There is provided a power amplifying device having a linearizer in which a bias circuit has an initial impedance set when initially operated, then the impedance is varied according to a level of an input signal and the input signal is amplified in a broad range from a low level region to a high level region, thereby improving linearity of an output signal. The power amplifying device including: an amplifying unit receiving a bias power source and amplifying an input signal; a bias unit varying the bias power source according to a set impedance to provide to the amplifying unit; and an impedance setting unit setting the impedance of the bias unit in response to a preset control voltage when the bias unit is initially operated and re-setting the impedance of the bias unit according to a level of the input signal of the amplifying unit after initial operation of the bias unit.

摘要翻译： 提供一种功率放大装置，其具有线性化装置，其中偏置电路在初始操作时具有设定的初始阻抗，然后根据输入信号的电平来改变阻抗，并且输入信号在低范围内被放大 电平区域到高电平区域，从而提高输出信号的线性度。 功率放大装置包括：放大单元，接收偏置电源并放大输入信号; 偏置单元根据设定的阻抗改变偏置电源以提供给放大单元; 以及阻抗设定单元，当偏置单元初始操作时，响应于预设的控制电压来设定偏置单元的阻抗，并根据放大单元的输入信号的电平在初始化之后重新设置偏置单元的阻抗 偏置单元的操作。

公开(公告)号：US07649431B2

公开(公告)日：2010-01-19

申请号：US11905786

申请日：2007-10-04

申请人： Yun Hee Cho ,  Yun Hwi Park

发明人： Yun Hee Cho ,  Yun Hwi Park

IPC分类号： H03H7/00 ,  H01P7/00

CPC分类号： H01P1/20345

摘要： There is provided a multi-layered band pass filter capable of improving a stop characteristic out of a pass band and reducing the entire size of the filter. The multi-layered band pass filter includes a ceramic laminated body having at least first to fifth dielectric layers laminated sequentially therein; first and second resonators having symmetrical patterns of first and second inductors formed on the first dielectric layer, and symmetrical patterns of first and second capacitors formed on the second dielectric layer so that they are at least partially overlapped with the patterns of the first and second inductors; a pattern of first and second load capacitors electrically capacitively coupled respectively to ends of the first and second resonators formed on the third dielectric layer; a pattern of first and second notching capacitors electrically capacitively coupled respectively to the other ends of the first and second resonators formed on the third dielectric layer; and first and second ground planes formed respectively on the fourth and fifth dielectric layers, wherein each of the patterns of the first and second inductors is composed of a low impedance portion formed of wide-width lines and a high impedance portion formed of meander-type narrow-width lines from the low impedance portion.

摘要翻译： 提供了能够改善通带中的停止特性并减小滤波器整体尺寸的多层带通滤波器。 多层带通滤波器包括：陶瓷层叠体，其中至少第一至第五电介质层依次层叠; 第一和第二谐振器具有形成在第一介电层上的第一和第二电感器的对称图案，以及形成在第二介电层上的第一和第二电容器的对称图案，使得它们至少部分地与第一和第二电感器的图案重叠 ; 第一和第二负载电容器的电容电容地耦合到形成在第三介电层上的第一和第二谐振器的端部; 分别与形成在第三电介质层上的第一和第二谐振器的另一端电容耦合的第一和第二开槽电容器的图案; 以及分别形成在第四和第五电介质层上的第一和第二接地层，其中第一和第二电感器的每个图案由宽宽线形成的低阻抗部分和由曲折形式形成的高阻抗部分 来自低阻抗部分的窄宽线。

公开(公告)号：US20070139129A1

公开(公告)日：2007-06-21

申请号：US11600063

申请日：2006-11-16

申请人： Yun Hwi Park

发明人： Yun Hwi Park

IPC分类号： H03K3/02

CPC分类号： H03F1/26 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H03F1/565 ,  H03F3/195 ,  H03F2200/222 ,  H03F2200/225 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/451 ,  H03H7/38 ,  H01L2924/00

摘要： In an RF balanced matching device, a first capacity pattern of a first area is formed on a first ceramic sheet. A second capacity pattern of a second area is formed on the first ceramic sheet, spaced apart from the first capacity pattern at a predetermined distance. A third capacity pattern of a third area is formed on a second ceramic sheet stacked on the first ceramic sheet, overlapping perpendicular to the first capacity pattern. The third capacity pattern cooperates with the first capacity pattern to form a first capacitance. Also, a fourth capacity pattern of a fourth area is formed on the second ceramic sheet, overlapping perpendicular to the second capacity pattern. The fourth capacity pattern cooperates with the second capacity pattern to form a second capacitance. An inductance pattern has a predetermined electrical length and connects the third capacity pattern with the fourth capacity pattern.

摘要翻译： 在RF平衡匹配装置中，在第一陶瓷片上形成第一区域的第一容量图案。 第二区域的第二容量图案形成在第一陶瓷片上，与第一容量图案间隔开预定距离。 第三区域的第三容量图案形成在堆叠在第一陶瓷片上的与第一容量图案垂直重叠的第二陶瓷片上。 第三容量模式与第一容量模式配合以形成第一电容。 此外，第四区域的第四容量图案形成在第二陶瓷片上，与第二电容图案垂直重叠。 第四容量模式与第二容量模式协调以形成第二电容。 电感图形具有预定的电长度，并将第三容量图与第四容量图形相连接。

公开(公告)号：US08637143B2

公开(公告)日：2014-01-28

申请号：US13004496

申请日：2011-01-11

申请人： Beom Joon Cho ,  Jong Myeon Lee ,  Yun Hwi Park

发明人： Beom Joon Cho ,  Jong Myeon Lee ,  Yun Hwi Park

IPC分类号： B32B18/00

CPC分类号： C04B35/117 ,  C03C14/004 ,  C03C2214/04 ,  C04B2235/36 ,  C04B2235/528 ,  C04B2235/5292 ,  C04B2235/5296 ,  C04B2235/5436 ,  C04B2235/5445 ,  C04B2235/787 ,  H01G4/129 ,  H01G4/30

摘要： There is provided a Low Temperature Co-fired Ceramic (LTCC) composition, an LTCC substrate comprising the same, and a method of manufacturing the same. The LTCC composition includes 20 to 70 parts by weight of ceramic powder; and 30 to 80 parts by weight of glass component for low-temperature sintering, wherein the ceramic powder has plate-shaped ceramic powder particles and globular ceramic powder particles, and the ceramic powder has a content ratio of the globular ceramic powder particles with respect to the plate-shaped ceramic powder particles in a range of 0 to 1.

摘要翻译： 提供了一种低温共烧陶瓷（LTCC）组合物，包含该组合物的LTCC基板及其制造方法。 LTCC组合物包含20至70重量份的陶瓷粉末; 和30〜80重量份的用于低温烧结的玻璃成分，其中陶瓷粉末具有板状陶瓷粉末颗粒和球状陶瓷粉末颗粒，陶瓷粉末的球形陶瓷粉末颗粒的含量相对于 板状陶瓷粉末颗粒的范围为0〜1。

公开(公告)号：US20130032383A1

公开(公告)日：2013-02-07

申请号：US13548575

申请日：2012-07-13

申请人： Won Hee Yoo ,  Byeung Gyu Chang ,  Taek Jung Lee ,  Yun Hwi Park

发明人： Won Hee Yoo ,  Byeung Gyu Chang ,  Taek Jung Lee ,  Yun Hwi Park

IPC分类号： H05K1/03 ,  B05D3/10

CPC分类号： H05K3/06 ,  H05K1/03 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/02 ,  H05K3/107 ,  H05K2201/0317 ,  H05K2203/025

摘要： Disclosed herein are a thin film electrode ceramic substrate and a method for manufacturing the same. The thin film electrode ceramic substrate includes: a ceramic substrate; one or more anti-etching metal layers formed in a surface of the ceramic substrate; thin film electrode pattern formed on the anti-etching metal layers; and a plating layer formed on the thin film electrode pattern, wherein respective edge portions of the thin film electrode pattern are contacted with the anti-etching metal layer, and thus, an undercut defect occurring between the surface of the ceramic substrate and the thin film electrode pattern and between the thin film electrode patterns due to an etchant can be prevented and the binding strength of the entire thin film electrode pattern can be enhanced, resulting in securing durability and reliability of the thin film electrode patterns.

摘要翻译： 本文公开了一种薄膜电极陶瓷基板及其制造方法。 薄膜电极陶瓷基板包括：陶瓷基板; 形成在陶瓷基板的表面上的一个或多个抗蚀刻金属层; 在抗蚀刻金属层上形成的薄膜电极图案; 以及形成在薄膜电极图案上的镀层，其中薄膜电极图案的各个边缘部分与抗蚀刻金属层接触，因此在陶瓷基板的表面和薄膜之间发生切削缺陷 可以防止由于蚀刻剂引起的薄膜电极图案之间的电极图案和薄膜电极图案之间的粘合强度，从而确保薄膜电极图案的耐久性和可靠性。