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    Semiconductor integrated circuit device
    1.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US5038193A

    公开(公告)日：1991-08-06

    申请号：US541751

    申请日：1990-06-21

    申请人： Yoshiaki Kamigaki ,  Shinichi Minami ,  Kazunori Furusawa ,  Yoshifumi Kawamoto ,  Shoji Shukuri ,  Masaaki Terasawa ,  Yasunori Ikeda ,  Hidefumi Mukohda

    发明人： Yoshiaki Kamigaki ,  Shinichi Minami ,  Kazunori Furusawa ,  Yoshifumi Kawamoto ,  Shoji Shukuri ,  Masaaki Terasawa ,  Yasunori Ikeda ,  Hidefumi Mukohda

    IPC分类号： H01L21/8247 ,  H01L21/76 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/105

    摘要： In the semiconductor integrated circuit device provided with a plurality of second well regions of the same conductivity type, formed by dividing a first well region provided in the semiconductor substrate by an isolation trench, the isolation trench is substantially linear on the semiconductor substrate surface and the ends reach out of the first well region, however there is no intersection part, namely a corner part T part or cross part in the isolation trench. Therefore, no cavity occurs in the filler in the trench and stress is not concentrated on the intersection part. In addition, defects due to junction leak or mechanical damage do not occur, that is, there is no characteristic deterioration occuring. By providing the second well with memory cell, a semiconductor memory device whose characteristic defect rate and reliability defect rate are remarkably low can be formed.

    摘要翻译： 在具有相同导电类型的多个第二阱区的半导体集成电路器件中，隔离沟槽在半导体衬底表面上是基本上线性的， 端部伸出第一阱区域，但是没有交叉部分，即隔离沟槽中的角部T部分或交叉部分。 因此，沟槽中的填料不会产生空穴，应力不集中在交叉部分上。 此外，不会发生由于接点泄漏或机械损伤引起的缺陷，即没有发生特性劣化。 通过向存储单元提供第二阱，可以形成其特性缺陷率和可靠性缺陷率非常低的半导体存储器件。

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5022000A

    公开(公告)日：1991-06-04

    申请号：US403372

    申请日：1989-09-06

    申请人： Masaaki Terasawa ,  Hidefumi Mukohda ,  Yoshikazu Nagai ,  Yasunori Ikeda ,  Kazunori Furusawa

    发明人： Masaaki Terasawa ,  Hidefumi Mukohda ,  Yoshikazu Nagai ,  Yasunori Ikeda ,  Kazunori Furusawa

    IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/08 ,  G11C16/12 ,  G11C16/30 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/30

    摘要： A writing high voltage of one polarity or an erasing high voltage of another polarity is selectively fed, in accordance with a writing or erasing operation mode, via a switch MOSFET to the word line of a non-volatile memory element designated by an address signal. The potential of a well region, where the switch MOSFET is existent, is changed in conformity with the switching action of the relevant switch MOSFET so as to control the switch MOSFET. Due to this arrangement, the potential of the well region with the non-volatile memory elements existing thereon can be retained at a fixed value, so that the high voltage generator is required merely to drive the selected word line of the memory array (and not the well in which the memory elements are formed). Consequently, the requisite current supply capability of the high voltage generator can be diminished.

    摘要翻译： 根据写入或擦除操作模式，通过开关MOSFET选择性地馈送一个极性的写入高电压或另一个极性的擦除高电压到由地址信号指定的非易失性存储器元件的字线。 存在开关MOSFET的阱区的电位根据相关开关MOSFET的开关动作而改变，从而控制开关MOSFET。 由于这种布置，存在于其上的非易失性存储元件的阱区的电位可以保持在固定值，使得高电压发生器仅需要驱动存储器阵列的选定字线（而不是 存储元件形成的井）。 因此，可以减少高压发电机所需的电流供应能力。

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4769787A

    公开(公告)日：1988-09-06

    申请号：US888072

    申请日：1986-07-22

    申请人： Kazunori Furusawa ,  Shinji Nabetani ,  Yoshiaki Kamigaki ,  Masaaki Terasawa

    发明人： Kazunori Furusawa ,  Shinji Nabetani ,  Yoshiaki Kamigaki ,  Masaaki Terasawa

    IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C17/00 ,  G11C11/34

    CPC分类号： G11C16/08 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14

    摘要： Using a comparatively low supply voltage of, e.g., +5V and a minus gate voltage, the voltage difference between the gate of an MNOS transistor and a P-type well region in which a MNOS transistor is formed is relatively changed to execute the writing and erasing of the MNOS transistor. Thus, the potential of an N-type semiconductor substrate can be fixed to a comparatively low potential, e.g., about +5V, so that a P-channel MOSFET formed on the semiconductor substrate operates with an ordinary signal level. Consequently, an EEPROM having peripheral circuits constructed of CMOS circuits can be provided. Accordingly, reduction in the power consumption of the EEPROM can be attained.

    摘要翻译： 使用例如+ 5V和负栅极电压的较低电源电压，MNOS晶体管的栅极与其中形成MNOS晶体管的P型阱区域之间的电压差相对变化，以执行写入和 擦除MNOS晶体管。 因此，N型半导体衬底的电位可以固定在比较低的电位，例如约+ 5V，使得形成在半导体衬底上的P沟道MOSFET以普通信号电平工作。 因此，可以提供具有由CMOS电路构成的外围电路的EEPROM。 因此，可以实现EEPROM的功耗的降低。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07449747B2

    公开(公告)日：2008-11-11

    申请号：US11311162

    申请日：2005-12-20

    申请人： Tomoyuki Ishii ,  Kazunori Furusawa ,  Hideaki Kurata ,  Yoshihiro Ikeda

    发明人： Tomoyuki Ishii ,  Kazunori Furusawa ,  Hideaki Kurata ,  Yoshihiro Ikeda

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C11/5621 ,  G11C16/0458 ,  G11C2211/5612 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/7887

    摘要： Flash memory is rapidly decreasing in price. There is a demand for a new memory system that permits size reduction and suits multiple-value memory. A flash memory of AND type suitable for multiple-value memory with multiple-level threshold values can be made small in area if the inversion layer is utilized as the wiring; however, it suffers the disadvantage of greatly varying in writing characteristics from cell to cell. Another promising method of realizing multiple-value memory is to change the storage locations. This method, however, poses a problem with disturbance at the time of operation. The present invention provides one way to realize a semiconductor memory device with reduced cell-to-cell variation in writing characteristics. The semiconductor memory has a source region and a drain region, which are formed parallel to each other, and an assist electrode which is between and parallel to the source and drain regions without overlapping, so that it uses, at the time of writing, the assist electrode as the assist electrode for hot electrons to be injected at the source side and it uses, at the time of reading, the inversion layer formed under the assist electrode as the source region or the drain region.

    摘要翻译： 闪存正在迅速降价。 需要一种允许大小缩小并适合多值内存的新内存系统。 如果使用反转层作为布线，则可以使适用于具有多级阈值的多值存储器的AND型闪速存储器的面积小; 然而，它具有从细胞到细胞的书写特征大大变化的缺点。 实现多值存储器的另一个有希望的方法是改变存储位置。 然而，这种方法在操作时存在干扰问题。 本发明提供了实现具有减小的写入特性的单元到单元变化的半导体存储器件的一种方式。 半导体存储器具有彼此平行形成的源极区域和漏极区域以及辅助电极，其在源极和漏极区域之间并且平行于其而不重叠，从而在写入时使用辅助电极 辅助电极作为用于在源极侧注入的热电子的辅助电极，并且在读取时使用形成在辅助电极下方的反型层作为源极区域或漏极区域。

    Memory card
    6.
    发明申请
    Memory card 有权
    存储卡

    公开(公告)号：US20050262292A1

    公开(公告)日：2005-11-24

    申请号：US11182956

    申请日：2005-07-18

    申请人： Kenji Kozakai ,  Yuusuke Jono ,  Motoki Kanamori ,  Kazunori Furusawa ,  Atsushi Shikata ,  Yosuke Yukawa

    发明人： Kenji Kozakai ,  Yuusuke Jono ,  Motoki Kanamori ,  Kazunori Furusawa ,  Atsushi Shikata ,  Yosuke Yukawa

    IPC分类号： G06K19/07 ,  G06F3/06 ,  G06F12/00 ,  G06F12/06 ,  G06F13/00 ,  G11C16/04 ,  G11C16/16 ,  G11C29/00

    CPC分类号： G11C16/16 ,  G06F3/0614 ,  G06F3/0626 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0416

    摘要： A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.

    摘要翻译： 存储卡（1）包括电可重写非易失性存储器（4），具有执行指令的功能的数据处理器（3），以及管理非易失性存储器中文件数据的分配，接口控制电路 2）具有建立外部接口的功能，用于响应于外部命令控制数据处理器执行指令并且用于控制对非易失性存储器的访问以及用于临时存储文件数据的缓冲存储器（7）。 接口控制电路包括用于对外部提供的第一命令进行解码并指示数据处理器从缓冲存储器获取指令并进行操作的命令控制装置。

    Memory card having a buffer memory for storing testing instruction
    8.
    发明授权
    Memory card having a buffer memory for storing testing instruction 失效
    具有用于存储测试指令的缓冲存储器的存储卡

    公开(公告)号：US07002853B2

    公开(公告)日：2006-02-21

    申请号：US10874381

    申请日：2004-06-24

    申请人： Kenji Kozakai ,  Yuusuke Jono ,  Motoki Kanamori ,  Kazunori Furusawa ,  Atsushi Shikata ,  Yosuke Yukawa

    发明人： Kenji Kozakai ,  Yuusuke Jono ,  Motoki Kanamori ,  Kazunori Furusawa ,  Atsushi Shikata ,  Yosuke Yukawa

    IPC分类号： G11C16/04

    CPC分类号： G11C16/16 ,  G06F3/0614 ,  G06F3/0626 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0416

    摘要： A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.

    摘要翻译： 存储卡（1）包括电可重写非易失性存储器（4），具有执行指令的功能的数据处理器（3），以及管理非易失性存储器中文件数据的分配，接口控制电路 2）具有建立外部接口的功能，用于响应于外部命令控制数据处理器执行指令并且用于控制对非易失性存储器的访问以及用于临时存储文件数据的缓冲存储器（7）。 接口控制电路包括用于对外部提供的第一命令进行解码并指示数据处理器从缓冲存储器获取指令并进行操作的命令控制装置。

    Memory card having a buffer memory for storing testing instruction
    9.
    发明授权
    Memory card having a buffer memory for storing testing instruction 有权
    具有用于存储测试指令的缓冲存储器的存储卡

    公开(公告)号：US06643725B1

    公开(公告)日：2003-11-04

    申请号：US09495955

    申请日：2000-02-02

    申请人： Kenji Kozakai ,  Yuusuke Jono ,  Motoki Kanamori ,  Kazunori Furusawa ,  Atsushi Shikata ,  Yosuke Yukawa

    发明人： Kenji Kozakai ,  Yuusuke Jono ,  Motoki Kanamori ,  Kazunori Furusawa ,  Atsushi Shikata ,  Yosuke Yukawa

    IPC分类号： G06F1300

    CPC分类号： G11C16/16 ,  G06F3/0614 ,  G06F3/0626 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0416

    摘要： A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.

    摘要翻译： 存储卡（1）包括电可重写非易失性存储器（4），具有执行指令并管理非易失性存储器中的文件数据分配的功能的数据处理器（3），接口控制电路 ）具有建立外部接口的功能，用于响应于外部命令控制数据处理器执行指令并且用于控制对非易失性存储器的访问以及用于临时存储文件数据的缓冲存储器（7）。 接口控制电路包括用于对外部提供的第一命令进行解码并指示数据处理器从缓冲存储器获取指令并进行操作的命令控制装置。

    Batch erasable nonvolatile memory device and erasing method
    10.
    发明授权
    Batch erasable nonvolatile memory device and erasing method 失效
    批量可擦除非易失性存储器件和擦除方法

    公开(公告)号：US5598368A

    公开(公告)日：1997-01-28

    申请号：US445105

    申请日：1995-05-19

    申请人： Masahito Takahashi ,  Michiko Odagiri ,  Takeshi Furuno ,  Kazunori Furusawa ,  Masashi Wada

    发明人： Masahito Takahashi ,  Michiko Odagiri ,  Takeshi Furuno ,  Kazunori Furusawa ,  Masashi Wada

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/16 ,  G11C16/34 ,  G11C13/00

    CPC分类号： G11C16/3477 ,  G11C16/16 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3468

    摘要： A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by a ejecting an electric charge accumulated at floating gates by program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells of said erase unit with a relatively small energy under a relatively small erase reference voltage, or is provided with an automatic erasing circuit for executing these operations.

    摘要翻译： 批量可擦除非易失性存储装置和使用该存储器单元的装置，该存储单元适于通过通过编程操作（包括预写操作）弹出在浮动栅极上累积的电荷来执行擦除操作， 序列，用于读取擦除单元的存储单元并且在不存储电荷的浮动栅极上对那些非易失性存储单元执行预写操作的第一操作，用于在存储单元中执行批量擦除操作的第二操作 在相对较大的擦除参考电压下具有相对大的能量的所述擦除单元的非易失性存储单元的高速度，用于执行所有擦除的非易失性存储单元的读操作的第三操作和对那些非易失性存储单元的写操作 适于具有相对低的阈值电压，以及第四操作，用于以低速执行批量擦除操作 所述擦除单元的非易失性存储单元在相对小的擦除参考电压下具有相对小的能量，或者设置有用于执行这些操作的自动擦除电路。