公开(公告)号：US4741333A

公开(公告)日：1988-05-03

申请号：US8965

申请日：1987-01-30

申请人： Yoshinobu Suzuki ,  Shusaku Nisiate ,  Kenzo Sato ,  Masakazu Ueno ,  Hiroaki Shimizu ,  Katsunori Fujimura

发明人： Yoshinobu Suzuki ,  Shusaku Nisiate ,  Kenzo Sato ,  Masakazu Ueno ,  Hiroaki Shimizu ,  Katsunori Fujimura

IPC分类号： F24F5/00 ,  A41D13/00 ,  A41D13/12 ,  A62B17/04 ,  A41D19/00 ,  A62B18/00

CPC分类号： A41D13/1209 ,  Y10S128/91

摘要： A dust-free garment including: a garment body having garment opening portions opening to the outside; an air passage system, attached to the garment body and having an outlet adapted to communicate to a dust collector for exhausting air therein to the dust collector to filter air; and an air entrance mechanism located in the vicinity of at least one of the garment opening portions and communicated to the air passage system for entering air into the air passage system.

公开(公告)号：US20080272329A1

公开(公告)日：2008-11-06

申请号：US11884930

申请日：2006-02-22

申请人： Atsushi Ito ,  Yoshiya Matsuno ,  Haruhide Shikano ,  Takahiko Ido ,  Takuo Matsuyama ,  Shigeo Fukuyasu ,  Masakazu Ueno

发明人： Atsushi Ito ,  Yoshiya Matsuno ,  Haruhide Shikano ,  Takahiko Ido ,  Takuo Matsuyama ,  Shigeo Fukuyasu ,  Masakazu Ueno

IPC分类号： C04B35/462

CPC分类号： H01L41/187 ,  C04B35/491 ,  C04B35/6261 ,  C04B2235/3213 ,  C04B2235/3251 ,  C04B2235/3284 ,  C04B2235/5445

摘要： The present invention provides a piezoelectric ceramic composition, for producing piezoelectric elements exhibiting high piezoelectric strain constant d33 and high Curie temperature Tc, which composition includes a perovskite PbZrO3 (a), a perovskite PbTiO3 (b), SrO (c), Nb2O5 (d) and ZnO (e), and relative amounts of the components (a), (b), (c) (d) and (e) satisfy the general formula: Pb(ZraTi1-a)O3+bSrO+cNbO2.5+dZnO wherein 0.51≦a≦0.54; 1.1×10−2≦b≦6.0×10−2; 0.9×10−2≦c≦4.25×10−2; 0.1×10−2≦d≦1.25×10−2; and 2.9≦c/d≦15.0.

摘要翻译： 本发明提供一种压电陶瓷组合物，其用于制造表现出高压电应变常数d 33和高居里温度Tc的压电元件，该组成包括钙钛矿PbZrO 3（a） ，钙钛矿型PbTiO 3（b），SrO（c），Nb 2 O 5（d）和ZnO（e），以及相对 组分（a），（b），（c）（d）和（e）的量满足通式：<？in-line-formula description =“In-line Formulas”end =“lead”？> Pb （Zr a a 1 a a-a）O 3 + bSrO + cNbO 2.5 + dZnO <βin-line -formulae description =“In-line Formulas”end =“tail”？>其中0.51 <= a <= 0.54; 1.1×10 -2 <= b <= 6.0×10 -2; 0.9×10 -2≤= c <= 4.25×10 -2; 0.1×10 -2 <= d <= 1.25×10 -2; 和2.9 <= c / d <= 15.0。

公开(公告)号：US5159433A

公开(公告)日：1992-10-27

申请号：US510468

申请日：1990-04-18

申请人： Akira Kazami ,  Osamu Nakamoto ,  Hisashi Shimizu ,  Katsumi Ohkawa ,  Yasuhiro Koike ,  Koji Nagahama ,  Masao Kaneko ,  Masakazu Ueno ,  Yasuo Saitou

发明人： Akira Kazami ,  Osamu Nakamoto ,  Hisashi Shimizu ,  Katsumi Ohkawa ,  Yasuhiro Koike ,  Koji Nagahama ,  Masao Kaneko ,  Masakazu Ueno ,  Yasuo Saitou

IPC分类号： H01L21/00 ,  H01L25/16 ,  H05K1/14 ,  H05K1/18

CPC分类号： H01L21/67126 ,  H01L21/67121 ,  H01L25/162 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/09701 ,  H01L2924/3025 ,  H05K1/141 ,  H05K1/18

摘要： In a position closest to the mounting position of a microcomputer in a casing of a hybrid integrated circuit device on which is mounted the microcomputer and its peripheral circuit elements, an insertion hole is formed for a non-volatile memory which feeds data to the microcomputer. A socket for connecting the non-volatile memory is provided at the bottom of this insertion hole. Because of this configuration it is possible to connect the microcomputer and the non-volatile memory at an extremely short distance and the mounting efficiency of the integrated circuit device is increased. In addition, the non-volatile memory can detachably be mounted. Furthermore, the external shape of the insertion hole for the non-volatile memory is essentially the same as the external shape of the non-volatile memory so that when the non-volatile memory is inserted, the entire surface of this hybrid integrated circuit device is almost flat, providing excellent handling characteristics.

公开(公告)号：US4578696A

公开(公告)日：1986-03-25

申请号：US554656

申请日：1983-11-23

申请人： Masakazu Ueno ,  Takeshige Ichimura

发明人： Masakazu Ueno ,  Takeshige Ichimura

IPC分类号： H01L31/04 ,  H01L21/205 ,  H01L29/04 ,  H01L31/0392 ,  H01L31/075 ,  H01L31/06

CPC分类号： H01L29/04 ,  H01L21/02532 ,  H01L21/02576 ,  H01L31/03921 ,  H01L31/075 ,  Y02E10/548 ,  Y10S438/936

摘要： A thin film semiconductor device and a method for manufacturing such a device containing a thin film semiconductor layer in which there is no misalignment between a semiconductor layer containing a microcrystalline phase and an adjacent layer having no such phase. A junction region is interposed between the two amorphous semiconductor layers having a microcrystalline phase content which varies gradually from the content of the amorphous semiconductor layer having no microcrystalline phase to that of the layer having a microcrystalline phase. The junction region may be formed by the use of a glow discharge decomposition technique wherein the discharge power is gradually varied.

摘要翻译： 一种薄膜半导体器件及其制造方法，该器件含有薄膜半导体层，其中在含有微晶相的半导体层与不具有这种相的相邻层之间不存在未对准。 在具有从不具有微晶相的非晶半导体层的含量与具有微晶相的层的含量逐渐变化的微晶相含量的两个非晶半导体层之间插入接合区域。 可以通过使用放电功率逐渐变化的辉光放电分解技术来形成结区域。

公开(公告)号：US20090086458A1

公开(公告)日：2009-04-02

申请号：US12233722

申请日：2008-09-19

申请人： Masashi Terauchi ,  Yoshiaki Kurosu ,  Masakazu Ueno ,  Norio Okazaki ,  Kazumasa Arai

发明人： Masashi Terauchi ,  Yoshiaki Kurosu ,  Masakazu Ueno ,  Norio Okazaki ,  Kazumasa Arai

IPC分类号： H05K7/06

CPC分类号： G09G3/296 ,  H01L24/45 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/451 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0295 ,  H05K1/053 ,  H05K1/111 ,  H05K2201/09954 ,  H05K2201/10166 ,  H01L2924/00 ,  H01L2224/05599

摘要： In plasma displays in different inch sizes, there is a disadvantage in that because each of the plasma displays in different inch sizes has an output semiconductor device with a different outer shape, a pitch of the external lead and the number of the output semiconductor devices vary, so that printed circuit boards need be designed differently for the different inch sizes. A hybrid integrated circuit includes mounting portions which are composed of a conductive path on an insulated metal substrate, and into which at least an output semiconductor device of a discharge maintaining circuit is incorporated, and includes external terminals arranged at a constant pitch. When the inch size of the plasma display is changed, the mounting portions are designed to have a size enough to accommodate the output semiconductor device for the greatest inch size. Thus, the same hybrid integrated circuit is commonly used.

摘要翻译： 在不同英寸尺寸的等离子体显示器中，存在的缺点在于，因为不同英寸尺寸的等离子体显示器具有不同外形的输出半导体器件，外部引线的间距和输出半导体器件的数量变化 ，因此不同英寸尺寸的印刷电路板需要不同的设计。 混合集成电路包括由绝缘金属基板上的导电路径构成的安装部，并且至少包括放电维持电路的输出半导体装置，并且包括以恒定间距排列的外部端子。 当等离子体显示器的英制尺寸改变时，安装部分被设计成具有足以容纳最大英寸尺寸的输出半导体器件的尺寸。 因此，通常使用相同的混合集成电路。

公开(公告)号：US4737852A

公开(公告)日：1988-04-12

申请号：US864036

申请日：1986-05-16

申请人： Hitoshi Dohkoshi ,  Masakazu Ueno ,  Toshiaki Kato

发明人： Hitoshi Dohkoshi ,  Masakazu Ueno ,  Toshiaki Kato

IPC分类号： H01L27/146 ,  H04N1/028 ,  H04N1/031 ,  H04N3/12 ,  H04N3/14

CPC分类号： H04N1/031 ,  H01L27/14665 ,  H04N3/127

摘要： An image sensor of the kind which employs a line array of a-Si photodiodes on an insulating substrate and in which the outputs of the diodes are stored in the lead capacitances until readout. To increase the size of the lead capacitance and thereby to improve the linearity of the ouput, the lead between each diode and its processing circuit is made one plate of a capacitor, of which the other plate is a metal film insulated from the lead and advantageously maintained at ground.

摘要翻译： 在绝缘基板上采用a-Si光电二极管的线阵列并且其中二极管的输出被存储在引线电容中直到读出的类型的图像传感器。 为了增加引线电容的尺寸，从而提高输出的线性，每个二极管与其处理电路之间的引线被制成电容器的一个板，另一个板是与引线绝缘的金属膜，有利地 保持在地面。

公开(公告)号：USD345963S

公开(公告)日：1994-04-12

申请号：US876211

申请日：1992-04-29

申请人： Masahito Kanaya ,  Masakazu Ueno ,  Kenichi Kobayashi

设计人： Masahito Kanaya ,  Masakazu Ueno ,  Kenichi Kobayashi

公开(公告)号：US5285107A

公开(公告)日：1994-02-08

申请号：US510467

申请日：1990-04-18

申请人： Akira Kazami ,  Osamu Nakamoto ,  Hisashi Shimizu ,  Katsumi Ohkawa ,  Yasuhiro Koike ,  Koji Nagahama ,  Masao Kaneko ,  Masakazu Ueno ,  Yasuo Saitou

发明人： Akira Kazami ,  Osamu Nakamoto ,  Hisashi Shimizu ,  Katsumi Ohkawa ,  Yasuhiro Koike ,  Koji Nagahama ,  Masao Kaneko ,  Masakazu Ueno ,  Yasuo Saitou

IPC分类号： H01L21/00 ,  H01L25/16 ,  H05K1/14 ,  H05K1/18 ,  H01L23/02 ,  H01L23/12

CPC分类号： H01L21/67126 ,  H01L21/67121 ,  H01L25/162 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/01014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/3025 ,  H05K1/141 ,  H05K1/189

摘要： A hybrid integrated circuit device is provided with: a microcomputer, a plurality of peripheral circuit elements, and a non-volatile memory which is positioned adjacent to the microcomputer, all of which are interconnected by a plurality of specified conductive paths; pair of integrated circuit substrates on which is formed the conductive paths and a casing provided with the pair of integrated circuit substrates secured to the upper and lower surfaces of the casing, forming a sealed space between these surfaces. The microcomputer and the peripheral circuit elements are positioned in the sealed space and only the non-volatile memory is positioned in an exposed space. The hybrid integrated circuit device of the present invention has a compact and simple form with a high degree of mounting density as well as superior handling capabilities and reliability.

摘要翻译： 混合集成电路装置具有：微型计算机，多个外围电路元件和位于微型计算机附近的非易失性存储器，所有这些都通过多个指定的导电路径相互连接; 一对集成电路基板，其上形成有导电路径，并且壳体设置有固定到壳体的上表面和下表面的一对集成电路基板，在这些表面之间形成密封空间。 微型计算机和外围电路元件位于密封空间中，只有非易失性存储器位于暴露的空间中。 本发明的混合集成电路器件具有紧凑且简单的形式，具有高度的安装密度以及优异的处理能力和可靠性。

公开(公告)号：US4656109A

公开(公告)日：1987-04-07

申请号：US777506

申请日：1985-09-19

申请人： Masakazu Ueno

发明人： Masakazu Ueno

IPC分类号： G01J3/50 ,  G01J3/51 ,  H01L31/0216 ,  H01L31/075 ,  H01L31/076

CPC分类号： H01L31/076 ,  G01J3/51 ,  H01L31/02165 ,  G01J2003/516 ,  Y02E10/548

摘要： A color photosensitive device includes a transparent base plate and a lamination of alternate layers of transparent conductive films and photoelectric conversion layers. The photoelectric conversion layers are sensitive to light of increasing wavelength as the distance from the base plate increases. The photoelectric conversion layers comprise amorphous silicone and the transparent conductive films comprise an oxide of indium, tin, or the like.

摘要翻译： 彩色感光装置包括透明基板和交替层的透明导电膜和光电转换层的叠层。 随着距离基板的距离增加，光电转换层对波长增加的光敏感。 光电转换层包括无定形硅氧烷，并且透明导电膜包括铟，锡等的氧化物。

公开(公告)号：US4634883A

公开(公告)日：1987-01-06

申请号：US699432

申请日：1985-02-07

申请人： Masaharu Nishiura ,  Masakazu Ueno

发明人： Masaharu Nishiura ,  Masakazu Ueno

IPC分类号： H01L27/146 ,  H01L31/105 ,  H03K17/94 ,  H04N1/193 ,  H01J40/14

CPC分类号： H04N1/193 ,  H01L27/14643 ,  H01L31/1055 ,  H03K17/943

摘要： An image sensor for use in a solid-state facsimile transmitter includes a plurality of photosensors disposed in an array, each photosensor composed of a plurality of series-connected photodiodes; a voltage source; a plurality of switches for selectively applying a reverse bias from the voltage source to the photosensor array, each photosensor in the array being successively reverse biased by a corresponding one of the switches; and an output resistor for detecting current flowing through the selected reverse biased photosensor. The photosensors and switches may each comprise a plurality of series-connected photodiodes provided on a common substrate.

摘要翻译： 用于固态传真发射机的图像传感器包括：阵列中布置的多个光电传感器，每个光电传感器由多个串联连接的光电二极管组成; 电压源; 多个开关，用于选择性地将来自电压源的反向偏压施加到光电传感器阵列，阵列中的每个光电传感器被相应的一个开关相继反向偏置; 以及用于检测流过所选择的反向偏置光电传感器的电流的输出电阻器。 光电传感器和开关可以各自包括设置在公共基板上的多个串联连接的光电二极管。