公开(公告)号：US5040034A

公开(公告)日：1991-08-13

申请号：US465748

申请日：1990-01-18

申请人： Yoshinori Murakami ,  Teruyoshi Mihara ,  Tsutomu Matsushita ,  Kenji Yao ,  Norihiko Kiritani

发明人： Yoshinori Murakami ,  Teruyoshi Mihara ,  Tsutomu Matsushita ,  Kenji Yao ,  Norihiko Kiritani

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L29/7839 ,  Y10S257/902

摘要： A semiconductor device includes a semiconductor substrate as a drain region. A metal source region is located on a first surface of the substrate. The metal and the substrate constitute a Schottky junction. An insulated gate, including a gate electrode and an insulating film surrounding the gate electrode, is adjacent to the Schottky junction, such that angle formed by the Schottky junction and the insulated gate in the substrate is an acute angle. A part of the Schottky metal can be buried in the form of a pillar in the substrate, and a channel region of the Schottky junction can be formed on the pillar near the insulated gate.

摘要翻译： 半导体器件包括作为漏极区域的半导体衬底。 金属源区位于基板的第一表面上。 金属和衬底构成肖特基结。 包括栅电极和围绕栅电极的绝缘膜的绝缘栅极与肖特基结相邻，使得由肖特基结和衬底中的绝缘栅极形成的角度是锐角。 肖特基金属的一部分可以以衬底的形式被埋入，并且可以在绝缘栅极附近的柱上形成肖特基结的沟道区。

公开(公告)号：USRE35405E

公开(公告)日：1996-12-17

申请号：US288731

申请日：1994-08-12

申请人： Yoshinori Murakami ,  Teruyoshi Mihara

发明人： Yoshinori Murakami ,  Teruyoshi Mihara

IPC分类号： H01L21/335 ,  H01L21/336 ,  H01L29/423 ,  H01L29/772 ,  H01L29/78 ,  H01L21/338

CPC分类号： H01L29/66416 ,  H01L29/66666 ,  H01L29/7722 ,  H01L29/7827 ,  H01L29/4232 ,  H01L29/4238 ,  Y10S148/05

摘要： A method of manufacturing semiconductor devices by forming a U-shaped insulated gate on a substrate, etching the substrate to expose a sidewall of the U-shaped insulated gate, covering the exposed part with a masking material, forming the sidewall of the masking material only adjoining to the exposed U-shaped insulated gate, etching the substrate vertically to form a groove, forming a semiconductor region on the groove and burying a metal into the groove.

摘要翻译： 一种通过在衬底上形成U形绝缘栅来制造半导体器件的方法，蚀刻衬底以露出U形绝缘栅极的侧壁，用掩模材料覆盖暴露部分，仅形成掩模材料的侧壁 邻接于暴露的U形绝缘栅极，垂直蚀刻衬底以形成沟槽，在沟槽上形成半导体区域并将金属埋入槽中。

公开(公告)号：US5132238A

公开(公告)日：1992-07-21

申请号：US631928

申请日：1990-12-20

申请人： Yoshinori Murakami ,  Teruyoshi Mihara

发明人： Yoshinori Murakami ,  Teruyoshi Mihara

IPC分类号： H01L21/335 ,  H01L21/336 ,  H01L29/423 ,  H01L29/772 ,  H01L29/78

CPC分类号： H01L29/66416 ,  H01L29/66666 ,  H01L29/7722 ,  H01L29/7827 ,  H01L29/4232 ,  H01L29/4238 ,  Y10S148/05

摘要： A method of manufacturing semiconductor devices by forming a U-shaped insulated gate on a substrate, etching the substrate to expose a sidewall of the U-shaped insulated gate, covering the exposed part with a masking material, forming the sidewall of the masking material only adjoining to the exposed U-shaped insulated gate, etching the substrate vertically to form a groove, forming a semiconductor region on the groove and burying a metal into the groove.

摘要翻译： 一种通过在衬底上形成U形绝缘栅来制造半导体器件的方法，蚀刻衬底以露出U形绝缘栅极的侧壁，用掩模材料覆盖暴露部分，仅形成掩模材料的侧壁 邻接于暴露的U形绝缘栅极，垂直蚀刻衬底以形成沟槽，在沟槽上形成半导体区域并将金属埋入槽中。

公开(公告)号：US5049953A

公开(公告)日：1991-09-17

申请号：US465750

申请日：1990-01-18

申请人： Teruyoshi Mihara ,  Kenji Yao ,  Tsutomu Matsushita ,  Yoshinori Murakami

发明人： Teruyoshi Mihara ,  Kenji Yao ,  Tsutomu Matsushita ,  Yoshinori Murakami

IPC分类号： H01L29/739 ,  H01L29/78 ,  H01L29/48 ,  H01L27/02 ,  H01L29/10 ,  H01L29/34

CPC分类号： H01L29/7839 ,  Y10S257/902

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, in which a drain region is formed in the substrate, and a gate electrode is formed on the surface of the substrate via an insulating film formed thereon. A Schottky metal as a source region is formed in the surface of the substrate away from the drain region, the Schottky metal and the substrate constituting a Schottky junction at an interface therebetween near the gate electrode. A shield layer of a second conductivity type is interposed between the Schottky metal and the substrate except in the Schottky junction. The gate electrode controls tunnel current at the Schottky junction.

摘要翻译： 半导体器件包括：第一导电类型的半导体衬底，其中在衬底中形成漏极区，并且通过形成在其上的绝缘膜在衬底的表面上形成栅电极。 作为源极区域的肖特金属金属在远离漏极区域的肖特基金属和衬底的与栅极电极附近的界面处构成肖特基结的表面上形成。 第二导电类型的屏蔽层介于除了肖特基结之外的肖特基金属和基板之间。 栅电极控制肖特基结的隧道电流。

公开(公告)号：US20060022307A1

公开(公告)日：2006-02-02

申请号：US11189886

申请日：2005-07-27

申请人： Yoshinori Murakami

发明人： Yoshinori Murakami

IPC分类号： H01L27/108

CPC分类号： H01L23/051 ,  H01L23/3735 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2924/014

摘要： A semiconductor package has: a semiconductor chip having first and second main electrodes arranged on two principal surfaces being opposite to each other; a first main wiring plate connected to the first main electrode and having a first external connection terminal; a second main wiring plate connected to the second main electrode and having a second external connection terminal; a first shell connected through an insulating film to at least a part of a second principal surface of the first main wiring plate, the second principal surface of the first main wiring plate being opposite to a first principal surface of the first main wiring plate that is connected to the first electrode; and a second shell connected through an insulating film to at least a part of a second principal surface of the second main wiring plate, the second principal surface of the second main wiring plate being opposite to a first principal surface of the second main wiring plate that is connected to the second electrode. The first principal surfaces of the first and second main wiring plates are adjacent to and parallel to each other except at the locations where the first and second main wiring plates are connected to the semiconductor chip and the locations where the first and second external connection terminals are formed.

公开(公告)号：US20050259884A1

公开(公告)日：2005-11-24

申请号：US11130179

申请日：2005-05-17

申请人： Yoshinori Murakami ,  Hitoshi Hirohata

发明人： Yoshinori Murakami ,  Hitoshi Hirohata

IPC分类号： G06K9/36 ,  H04N1/405

CPC分类号： H04N1/4052

摘要： A quantization error calculation portion calculates the difference between the pixel value of a pixel of an input image added with an accumulative error by the adder and the quantization value obtained by quantizing the pixel value in the quantization processing portion as a quantization error. The quantization error is stored in the error storage portion. The multiplier multiplies, a quantization error to be distributed to a subsequently-quantized pixel, among the quantization errors stored in the error storage portion, by the diffusion coefficient numerator value corresponding to the quantization error. The adder adds the multiplication result produced by the multiplier. The divider divides the addition result produced by the adder by the diffusion coefficient denominator value. The division result is outputted to the adder as an accumulative error for a subsequently-quantized pixel.

摘要翻译： 量化误差计算部分计算由加法器添加的累积误差的输入图像的像素的像素值与通过量化量化处理部分中的像素值量化的量化值之间的差作为量化误差。 量化误差被存储在错误存储部分中。 通过与量化误差对应的扩散系数分子值，乘法器将存储在误差存储部分中的量化误差中的乘法器乘以要分配给后续量化像素的量化误差。 加法器加上由乘法器产生的相乘结果。 分频器将加法器产生的相加结果除以扩散系数分母值。 分割结果作为后续量化像素的累积误差输出到加法器。

公开(公告)号：US06930333B2

公开(公告)日：2005-08-16

申请号：US10883973

申请日：2004-07-06

申请人： Yoshinori Murakami

发明人： Yoshinori Murakami

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/495 ,  H01L23/498 ,  H01L29/417 ,  H01L29/74

CPC分类号： H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L29/41716 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/16152 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device wiring structure is provided to reduce the wiring inductance and curtail the generation of interfering electromagnetic waves. A semiconductor chip having an anode electrode and a cathode electrode provided on two oppositely-facing main surfaces is sandwiched between a sheet-shaped anode wiring and a sheet-shaped cathode wiring. The anode and cathode electrodes of the semiconductor chip are connected to the anode and the cathode wirings, respectively, arranged such that the electric currents flowing there-through flow in opposite directions. A conductive substrate having a main surface with a larger width than the cathode wiring is disposed adjacent to the anode wiring. The edges of the cathode wiring protrude beyond the edges of both the anode wiring and the semiconductor chip in all locations and the dimension of the protrusion is at least one half of the distance from the edge of the cathode wiring to the metal substrate.

公开(公告)号：US20050121783A1

公开(公告)日：2005-06-09

申请号：US10998990

申请日：2004-11-30

申请人： Yoshinori Murakami

发明人： Yoshinori Murakami

IPC分类号： H01L23/34 ,  H01L23/367 ,  H01L23/538 ,  H02M7/04 ,  H02M7/48 ,  H01L23/495

CPC分类号： H01L23/5386 ,  F28D15/0233 ,  H01L23/367 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device mounting structure includes a bus bar of which a first end part is connected to a high-temperature power-purpose semiconductor device and a second end is connected to another device that is required to be kept at a lower temperature than the semiconductor device. The bus bar includes a ribbonlike part zigzagging between the first and second ends. The ribbonlike part of the bus bar can improve the cooling effect by increasing the length of the path through which the heat travels in the lengthwise direction of the bus bar. Thus, the heat emitted from the semiconductor device is prevented from being transferred to a peripheral circuit element through the bus bar used for supplying electric power to the circuit element from the semiconductor device.

摘要翻译： 半导体器件安装结构包括母线，第一端部连接到高温电力半导体器件，第二端连接到需要保持在比半导体器件低的温度的另一器件 。 母线包括在第一和第二端之间曲折的带状部分。 汇流条的带状部分可以通过增加热量在汇流条的长度方向上行进的路径的长度来改善冷却效果。 因此，防止从半导体器件发出的热量通过用于从半导体器件向电路元件供电的汇流条传送到外围电路元件。

公开(公告)号：US06828506B2

公开(公告)日：2004-12-07

申请号：US10445037

申请日：2003-05-27

申请人： Yoshinori Murakami

发明人： Yoshinori Murakami

IPC分类号： H01B708

CPC分类号： H05K1/0216 ,  H01L23/5383 ,  H01L25/072 ,  H01L2924/0002 ,  H05K2201/09672 ,  H05K2201/09727 ,  H01L2924/00

摘要： A wiring or electrode structure is configured to reduce the wiring inductance of the power conductors in a semiconductor power module and prevent as much as possible the emission of interference electromagnetic waves. The wiring or electrode structure has an insulation layer that faces a main surface of a conductive base layer, a first conductor that faces the surface of the insulation layer, and a second conductor through which current flows in the opposite direction as the current that flows in the first conductor. The second electrical conductor overlying the first electrical conductor such opposite longitudinal edges of the second electrical conductor extend beyond corresponding longitudinal edges of the first electrical conductor at all locations by predetermined distances.

摘要翻译： 布线或电极结构被配置为减少半导体功率模块中的电力导体的布线电感，并尽可能地防止干扰电磁波的发射。 布线或电极结构具有面向导电基底层的主表面的绝缘层，面向绝缘层的表面的第一导体和电流沿相反方向流动的第二导体，作为流过电流的电流 第一个指挥。 覆盖第一电导体的第二电导体，第二电导体的相对纵向边缘延伸超过所有位置处第一电导体的相应纵向边缘预定距离。

公开(公告)号：US06641407B2

公开(公告)日：2003-11-04

申请号：US09955302

申请日：2001-09-19

申请人： Yoshinori Murakami

发明人： Yoshinori Murakami

IPC分类号： H01R1200

CPC分类号： H05K3/368 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2924/13091 ,  H01R12/52 ,  H05K1/0216 ,  H05K1/145 ,  H05K1/148 ,  H05K1/162 ,  H05K3/36 ,  H05K2201/0792 ,  H05K2201/09672 ,  H05K2201/1028 ,  H05K2201/10818 ,  H05K2201/10893 ,  H01L2924/00014 ,  H01L2924/00

摘要： An interconnect structure has a plurality of planar interconnects (1, 2) mutually superposed with a prescribed distance therebetween and serving as interconnects between two circuit boards (A, B), each of the planar interconnects (1, 2) having at least two connection terminals (1A, 1B, 2A, 2B) at the circuit boards (1, 2). Rather than using rigid wire interconnects as done in the past to make interconnections, planar interconnects having relatively large surface areas are used to increase the line-to-line capacitance, thereby enhancing the filtering function that reduces high-frequency noise.

摘要翻译： 互连结构具有多个平面互连（1,2），它们之间以规定距离相互重叠并且用作两个电路板（A，B）之间的互连，每个平面互连（1,2）具有至少两个连接 电路板（1,2）上的端子（1A，1B，2A，2B）。 不像以前那样使用刚性的电线互连来做互连，而是使用具有相对大的表面积的平面互连来增加线对线电容，从而增强降低高频噪声的滤波功能。