公开(公告)号：US20090045441A1

公开(公告)日：2009-02-19

申请号：US12078175

申请日：2008-03-27

申请人： Young Do Kweon ,  Sung Yi ,  Hong-Won Kim

发明人： Young Do Kweon ,  Sung Yi ,  Hong-Won Kim

IPC分类号： H01L31/113

CPC分类号： H01L27/14618 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00

摘要： A CMOS image sensor package is disclosed. The CMOS image sensor package includes: a substrate, on which a pre-designed circuit pattern is formed, and in which a cavity is formed; a pixel array sensor, which is electrically connected with the circuit pattern and stacked on one side of the substrate; and a control chip, which is electrically connected with the circuit pattern and held within the cavity. According to certain aspects of the invention, the CMOS image sensor chip can be separated into the pixel array sensor and the control chip, with the control chip and passive components embedded in cavities formed in the substrate, so that the size of the chip mounted on the substrate may be reduced, and consequently the overall size of the CMOS image sensor package may be reduced.

摘要翻译： 公开了CMOS图像传感器封装。 CMOS图像传感器封装包括：基板，其上形成有预先设计的电路图案，并且其中形成空腔; 像素阵列传感器，其与电路图案电连接并堆叠在基板的一侧上; 以及与电路图案电连接并保持在空腔内的控制芯片。 根据本发明的某些方面，CMOS图像传感器芯片可以分离成像素阵列传感器和控制芯片，其中控制芯片和无源部件嵌入到形成在基板中的空腔中，使得芯片的尺寸安装在 可以减小衬底，因此可以减小CMOS图像传感器封装的整体尺寸。

公开(公告)号：US08943685B2

公开(公告)日：2015-02-03

申请号：US12923992

申请日：2010-10-19

申请人： Young Do Kweon ,  Sung Yi ,  Hong-Won Kim

发明人： Young Do Kweon ,  Sung Yi ,  Hong-Won Kim

IPC分类号： H05K3/02 ,  H05K1/16 ,  H05K3/06 ,  H05K3/46

CPC分类号： H05K1/162 ,  H05K3/062 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09881 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A method of manufacturing a capacitor-embedded printed circuit board using a first conductive layer formed on one side of an insulation layer, the method including: forming a second conductive layer on one side of the first conductive layer; forming a second electrode by removing a portion of the second conductive layer; forming a first electrode by removing a portion of the first conductive layer in correspondence with the second electrode; and forming a dielectric layer on one side of the second electrode.

摘要翻译： 一种使用形成在绝缘层的一侧上的第一导电层制造电容器嵌入式印刷电路板的方法，所述方法包括：在所述第一导电层的一侧上形成第二导电层; 通过去除所述第二导电层的一部分来形成第二电极; 通过与所述第二电极对应地移除所述第一导电层的一部分来形成第一电极; 以及在所述第二电极的一侧上形成介电层。

公开(公告)号：US20110035938A1

公开(公告)日：2011-02-17

申请号：US12923992

申请日：2010-10-19

申请人： Young Do Kweon ,  Sung Yi ,  Hong-Won Kim

发明人： Young Do Kweon ,  Sung Yi ,  Hong-Won Kim

IPC分类号： H05K3/00

CPC分类号： H05K1/162 ,  H05K3/062 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09881 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A method of manufacturing a capacitor-embedded printed circuit board using a first conductive layer formed on one side of an insulation layer, the method including: forming a second conductive layer on one side of the first conductive layer; forming a second electrode by removing a portion of the second conductive layer; forming a first electrode by removing a portion of the first conductive layer in correspondence with the second electrode; and forming a dielectric layer on one side of the second electrode.

摘要翻译： 一种使用形成在绝缘层的一侧上的第一导电层制造电容器嵌入式印刷电路板的方法，所述方法包括：在所述第一导电层的一侧上形成第二导电层; 通过去除所述第二导电层的一部分来形成第二电极; 通过与所述第二电极对应地移除所述第一导电层的一部分来形成第一电极; 以及在所述第二电极的一侧上形成介电层。

公开(公告)号：US20090046409A1

公开(公告)日：2009-02-19

申请号：US12076651

申请日：2008-03-20

申请人： Young Do Kweon ,  Sung Yi ,  Hong-Won Kim

发明人： Young Do Kweon ,  Sung Yi ,  Hong-Won Kim

IPC分类号： H01G4/005 ,  H01G7/00

CPC分类号： H05K1/162 ,  H05K3/062 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09881 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A capacitor-embedded printed circuit board and a method of manufacturing the printed circuit board are disclosed. The capacitor-embedded printed circuit board includes: an insulation layer, a first electrode formed on one side of the insulation layer, a second electrode formed on one side of the first electrode, a dielectric layer formed on one side of the second electrode, and a third electrode formed on one side of the dielectric layer. By forming the electrodes of the capacitor in a dual structure, deviations in contact area may be minimized between the second electrode and the dielectric layer, so that ultimately, errors in capacitance may be reduced.

摘要翻译： 公开了电容器嵌入式印刷电路板和印刷电路板的制造方法。 电容器嵌入式印刷电路板包括：绝缘层，形成在绝缘层的一侧的第一电极，形成在第一电极的一侧上的第二电极，形成在第二电极的一侧的电介质层，以及 形成在电介质层一侧的第三电极。 通过以双重结构形成电容器的电极，可以在第二电极和电介质层之间使接触面积的偏差最小化，从而最终可能降低电容误差。

公开(公告)号：US20100320624A1

公开(公告)日：2010-12-23

申请号：US12547284

申请日：2009-08-25

申请人： Joon Seok KANG ,  Young Do Kweon ,  Hong Won Kim ,  Jingli Yuan

发明人： Joon Seok KANG ,  Young Do Kweon ,  Hong Won Kim ,  Jingli Yuan

IPC分类号： H01L23/28 ,  H01L23/522 ,  H01L21/56 ,  H01L21/50

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3171 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

摘要： Disclosed herein is a die package including an encapsulated die, including: a die including pads on one side thereof; an encapsulation layer covering lateral sides of the die; a support layer covering the encapsulation layer and one side of the die; a passivation layer formed on the other side of the die such that the pads are exposed therethrough; and a redistribution layer formed on the passivation layer such that one part thereof is connected with the pad. Here, since one side of the die is supported by the support layer and the encapsulation layer is formed on only the lateral side of the die, the warpage of the die package due to the difference in thermal expansion coefficient can be minimized.

摘要翻译： 本文公开了一种包括封装模具的模具封装，包括：一个模具，其在其一侧包括焊盘; 覆盖所述管芯的侧面的封装层; 覆盖该封装层和该芯片的一侧的支撑层; 钝化层，形成在所述管芯的另一侧上，使得所述焊盘暴露在其中; 以及形成在钝化层上的再分配层，使得其一部分与焊盘连接。 这里，由于模具的一侧由支撑层支撑，并且仅在模具的侧面形成封装层，所以可以将由于热膨胀系数的差异导致的模具封装的翘曲最小化。

公开(公告)号：US08334602B2

公开(公告)日：2012-12-18

申请号：US12547284

申请日：2009-08-25

申请人： Joon Seok Kang ,  Young Do Kweon ,  Hong Won Kim ,  Jingli Yuan

发明人： Joon Seok Kang ,  Young Do Kweon ,  Hong Won Kim ,  Jingli Yuan

IPC分类号： H01L29/72

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3171 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

摘要： Disclosed herein is a die package including an encapsulated die, including: a die including pads on one side thereof; an encapsulation layer covering lateral sides of the die; a support layer covering the encapsulation layer and one side of the die; a passivation layer formed on the other side of the die such that the pads are exposed therethrough; and a redistribution layer formed on the passivation layer such that one part thereof is connected with the pad. Here, since one side of the die is supported by the support layer and the encapsulation layer is formed on only the lateral side of the die, the warpage of the die package due to the difference in thermal expansion coefficient can be minimized.

摘要翻译： 本文公开了一种包括封装模具的模具封装，包括：一个模具，其在其一侧包括焊盘; 覆盖所述管芯的侧面的封装层; 覆盖该封装层和该芯片的一侧的支撑层; 钝化层，形成在所述管芯的另一侧上，使得所述焊盘暴露在其中; 以及形成在钝化层上的再分配层，使得其一部分与焊盘连接。 这里，由于模具的一侧由支撑层支撑，并且仅在模具的侧面形成封装层，所以能够将由于热膨胀系数的差异导致的模具封装的翘曲最小化。

公开(公告)号：US07663250B2

公开(公告)日：2010-02-16

申请号：US12230793

申请日：2008-09-04

申请人： Hyung Jin Jeon ,  Sung Yi ,  Jong Yun Lee ,  Young Do Kweon ,  Jong Hwan Baek

发明人： Hyung Jin Jeon ,  Sung Yi ,  Jong Yun Lee ,  Young Do Kweon ,  Jong Hwan Baek

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal.

摘要翻译： 一种晶片级封装及其制造方法，能够减少凸块之间的应力。 晶片级封装包括在顶表面上设置有多个芯片焊盘的衬底; 第一钝化层以暴露所述芯片焊盘; 通过穿过第一钝化层连接到芯片焊盘的通孔; 形成在所述第一钝化层上并连接到所述通孔的金属布线层; 形成在所述第一钝化层上以连接到所述金属布线层并且具有通过中心的沟槽分离的缓冲图案的下凸块金属; 形成在所述第一钝化层上以暴露所述下凸块金属的第二钝化层; 形成在缓冲图案上的第一凸起; 以及填充所述沟槽并形成在所述第一凸块和所述下凸块金属上的第二凸块。

公开(公告)号：US08283768B2

公开(公告)日：2012-10-09

申请号：US12424514

申请日：2009-04-15

申请人： Joon Seok Kang ,  Sung Yi ,  Young Do Kweon

发明人： Joon Seok Kang ,  Sung Yi ,  Young Do Kweon

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/4334 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01073 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： Disclosed herein are a wafer level package for heat dissipation and a method of manufacturing the same. The wafer level package includes a heat dissipation plate including a cavity and a hole, a die including a pad disposed in the cavity of the heat dissipation plate in a face-up manner, a thermal conductive adhesive disposed between the die and an inner wall of the cavity and disposed in the hole, and a redistribution layer connected at one end to the pad and at the other end extended. The wafer level package protects the die from external environments and enables the die to be easily flush with the heat dissipation plate.

摘要翻译： 这里公开了用于散热的晶片级封装及其制造方法。 晶片级封装包括包括空腔和孔的散热板，包括以面朝上的方式设置在散热板的空腔中的焊盘的模具，设置在模具和内壁之间的导热粘合剂 空腔并设置在孔中，并且再分配层在一端连接到垫并且在另一端延伸。 晶圆级封装保护模具免受外部环境的影响，使模具能够轻松地与散热板齐平。

公开(公告)号：US08026590B2

公开(公告)日：2011-09-27

申请号：US12581131

申请日：2009-10-17

申请人： Joon Seok Kang ,  Young Ho Kim ,  Young Do Kweon ,  Jin Gu Kim ,  Sung Yi

发明人： Joon Seok Kang ,  Young Ho Kim ,  Young Do Kweon ,  Jin Gu Kim ,  Sung Yi

IPC分类号： H01L23/488 ,  H01L21/58

CPC分类号： H01L21/561 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2924/00

摘要： Disclosed herein are a die package and a method of manufacturing the die package. A solder layer is formed on a lower surface of a die. The die is self-aligned and attached to a support plate using surface tension between the solder layer and a metal layer of the support plate, thus reducing attachment lead time of the die.

摘要翻译： 这里公开了一种管芯封装和制造该封装的方法。 在模具的下表面上形成焊料层。 使用焊料层和支撑板的金属层之间的表面张力将模具自对准并附接到支撑板，从而减少模具的附着时间。

公开(公告)号：US20110042799A1

公开(公告)日：2011-02-24

申请号：US12581131

申请日：2009-10-17

申请人： Joon Seok KANG ,  Young Ho Kim ,  Young Do Kweon ,  Jin Gu Kim ,  Sung Yi

发明人： Joon Seok KANG ,  Young Ho Kim ,  Young Do Kweon ,  Jin Gu Kim ,  Sung Yi

IPC分类号： H01L23/488 ,  H01L21/78

CPC分类号： H01L21/561 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2924/00

摘要： Disclosed herein are a die package and a method of manufacturing the die package. A solder layer is formed on a lower surface of a die. The die is self-aligned and attached to a support plate using surface tension between the solder layer and a metal layer of the support plate, thus reducing attachment lead time of the die.

摘要翻译： 这里公开了一种管芯封装和制造该封装的方法。 在模具的下表面上形成焊料层。 使用焊料层和支撑板的金属层之间的表面张力将模具自对准并附接到支撑板，从而减少模具的附着时间。