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    Gate oxide measurement apparatus
    1.
    发明授权
    Gate oxide measurement apparatus 有权
    栅极氧化物测量装置

    公开(公告)号：US06916671B2

    公开(公告)日：2005-07-12

    申请号：US10734044

    申请日：2003-12-11

    申请人： Yu-Chang Lin ,  Ming-Cheng Chang

    发明人： Yu-Chang Lin ,  Ming-Cheng Chang

    IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L21/8242 ,  H01L23/58 ,  H01L27/02

    CPC分类号： G01B7/08 ,  H01L27/0207 ,  H01L27/10864 ,  H01L27/10876

    摘要： An apparatus for measuring a gate oxide thickness comprises a first active area, first to fifth wordlines, first and second bar-shaped trench capacitors, and first and second gate structures. The first active area with a width of at least 2F is disposed on a substrate. The first to fifth wordline is disposed on the substrate in a first direction, with a first predetermined space between each two wordlines, and first ends of the first to fifth wordlines are electrically connected. The first and second bar-shaped trench capacitors are disposed under the second and the fourth wordlines respectively with a second predetermined space between the first and second bar-shaped trench capacitors, and F is a minimum line width of the wordlines. The first and second gate structure are respectively disposed between the first bar-shaped trench capacitor and the second wordline and between the second bar-shaped trench capacitor and the fourth wordline.

    摘要翻译： 用于测量栅极氧化物厚度的装置包括第一有源区，第一至第五字线，第一和第二条形沟槽电容器以及第一和第二栅极结构。 宽度为2F以上的第一有源区域设置在基板上。 第一至第五字线在第一方向上设置在基板上，每两个字线之间具有第一预定空间，并且第一至第五字线的第一端电连接。 第一和第二条形沟槽电容器分别设置在第二和第四字线下方，第一和第二条形沟槽电容器之间具有第二预定空间，F是字线的最小线宽。 第一和第二栅极结构分别设置在第一条形沟槽电容器和第二字线之间以及第二条形沟槽电容器和第四字线之间。

    Gate oxide measurement apparatus
    2.
    发明申请
    Gate oxide measurement apparatus 有权

    公开(公告)号：US20050045878A1

    公开(公告)日：2005-03-03

    申请号：US10734044

    申请日：2003-12-11

    申请人： Yu-Chang Lin ,  Ming-Cheng Chang

    发明人： Yu-Chang Lin ,  Ming-Cheng Chang

    IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L21/8242 ,  H01L23/58 ,  H01L27/02

    CPC分类号： G01B7/08 ,  H01L27/0207 ,  H01L27/10864 ,  H01L27/10876

    摘要： An apparatus for measuring a gate oxide thickness comprises a first active area, first to fifth wordlines, first and second bar-shaped trench capacitors, and first and second gate structures. The first active area with a width of at least 2F is disposed on a substrate. The first to fifth wordline is disposed on the substrate in a first direction, with a first predetermined space between each two wordlines, and first ends of the first to fifth wordlines are electrically connected. The first and second bar-shaped trench capacitors are disposed under the second and the fourth wordlines respectively with a second predetermined space between the first and second bar-shaped trench capacitors, and F is a minimum line width of the wordlines. The first and second gate structure are respectively disposed between the first bar-shaped trench capacitor and the second wordline and between the second bar-shaped trench capacitor and the fourth wordline.

    NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    4.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20100200903A1

    公开(公告)日：2010-08-12

    申请号：US12767639

    申请日：2010-04-26

    申请人： Ming-Cheng Chang ,  Chih-Hsiung Hung ,  Mao-Ying Wang ,  Wei-Hui Hsu

    发明人： Ming-Cheng Chang ,  Chih-Hsiung Hung ,  Mao-Ying Wang ,  Wei-Hui Hsu

    IPC分类号： H01L29/788

    CPC分类号： H01L29/66583 ,  H01L21/28273 ,  H01L29/512 ,  H01L29/7887

    摘要： A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

    摘要翻译： 提供一种非易失性存储器件及其制造方法。 非易失性存储器件的制造方法包括提供衬底。 在衬底中形成隧道绝缘层和第一导电层。 通过第一导电层和隧道绝缘层形成沟槽，其中衬底的一部分从沟槽露出。 在沟槽中形成第一绝缘层。 第二绝缘层形成在第一绝缘层的侧壁上。 第三绝缘层顺应地形成在沟槽中，覆盖沟槽底部的第一绝缘层和沟槽侧壁上的第二绝缘层，其中侧壁上的第三绝缘层的厚度比在 沟渠的底部。 控制栅极形成在沟槽中的第三绝缘层上。

    TWO-BIT FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME
    6.
    发明申请
    TWO-BIT FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    双位闪存存储器单元及其制造方法

    公开(公告)号：US20080265342A1

    公开(公告)日：2008-10-30

    申请号：US11780482

    申请日：2007-07-20

    申请人： Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Chien-Chang Huang

    发明人： Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Chien-Chang Huang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7923 ,  H01L29/40117 ,  H01L29/42348

    摘要： A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a T-shaped gate on the gate oxide layer. A first charge storage layer is disposed at one side of and under the T-shaped gate. A second charge storage layer, which is separated from the first charge storage layer by a bottom portion of the T-shaped gate and the gate oxide layer, is disposed at the other side of and under the T-shaped gate. An insulating layer is disposed between the T-shaped gate and the gate oxide layer. A first source/drain region is disposed at one side of the T-shaped gate within the substrate. A second source/drain region is disposed at the other side of the T-shaped gate within the substrate.

    摘要翻译： 两位闪存单元包括衬底，设置在衬底上的栅极氧化物层，栅极氧化物层上的T形栅极。 第一电荷存储层设置在T形门的一侧和下方。 通过T形栅极和栅极氧化物层的底部与第一电荷存储层分离的第二电荷存储层设置在T形栅极的另一侧和下方。 绝缘层设置在T形栅极和栅极氧化物层之间。 第一源极/漏极区域设置在衬底内的T形栅极的一侧。 第二源极/漏极区域设置在衬底内的T形栅极的另一侧。

    DYNAMIC RANDOM ACCESS MEMORY
    7.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY 有权
    动态随机存取存储器

    公开(公告)号：US20080029800A1

    公开(公告)日：2008-02-07

    申请号：US11696160

    申请日：2007-04-03

    申请人： Ming-Cheng Chang ,  Neng-Tai Shih

    发明人： Ming-Cheng Chang ,  Neng-Tai Shih

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10841 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10876

    摘要： A DRAM structure on a silicon substrate has an active area, gate conductors, deep trench capacitors, and vertical transistors. The deep trench capacitors are formed at intersections of the active area and the gate conductors, and each deep trench capacitor is coupled electrically to the corresponding vertical transistor to form a memory cell. The transistor includes a gate, a source in a lateral side of the gate, and a drain in another lateral side of the gate The depth of the drain is different from the depth of the source.

    摘要翻译： 硅衬底上的DRAM结构具有有源区，栅极导体，深沟槽电容器和垂直晶体管。 深沟槽电容器形成在有源区和栅极导体的交点处，并且每个深沟槽电容器电耦合到相应的垂直晶体管以形成存储单元。 晶体管包括栅极，栅极的侧面中的源极和栅极的另一侧面中的漏极漏极的深度不同于源极的深度。

    Partial vertical memory cell and method of fabricating the same
    8.
    发明授权
    Partial vertical memory cell and method of fabricating the same 有权
    部分垂直记忆单元及其制造方法

    公开(公告)号：US07033886B2

    公开(公告)日：2006-04-25

    申请号：US10998219

    申请日：2004-11-26

    申请人： Ming-Cheng Chang ,  Yi-Chen Chen ,  Yi-Nan Chen

    发明人： Ming-Cheng Chang ,  Yi-Chen Chen ,  Yi-Nan Chen

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/26586 ,  H01L27/10832 ,  H01L27/10838 ,  H01L27/10864 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/1037 ,  H01L29/78 ,  H01L29/945

    摘要： A partial vertical memory cell and fabrication method thereof. A semiconductor substrate is provided, in which two deep trenches having deep trench capacitors respectively are formed, and the deep trench capacitors are lower than a top surface of the semiconductor substrate. A portion of the semiconductor outside the deep trenches is removed to form a pillar between. The pillar is ion implanted to form an ion-doped area in the pillar corner acting as a S/D area. A gate dielectric layer and a conducting layer are conformally formed on the pillar sequentially. An isolation is formed in the semiconductor substrate beside the conducting layer. The conducting layer is defined to form a first gate and a second gate.

    摘要翻译： 局部垂直存储单元及其制造方法。 提供一种半导体衬底，其中分别形成具有深沟槽电容器的两个深沟槽，并且深沟槽电容器低于半导体衬底的顶表面。 在深沟槽外部的半导体的一部分被去除以在其之间形成柱。 柱被离子注入以在柱角中形成作为S / D区域的离子掺杂区域。 栅极电介质层和导电层依次形成在柱上。 在导电层旁边的半导体衬底中形成隔离。 导电层被限定为形成第一栅极和第二栅极。

    Memory device with vertical transistors and deep trench capacitors and method of fabricating the same
    10.
    发明申请
    Memory device with vertical transistors and deep trench capacitors and method of fabricating the same 有权
    具有垂直晶体管和深沟槽电容器的存储器件及其制造方法

    公开(公告)号：US20050167719A1

    公开(公告)日：2005-08-04

    申请号：US11068173

    申请日：2005-02-28

    申请人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

    发明人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

    CPC分类号： H01L27/10864 ,  H01L27/10867

    摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

    摘要翻译： 具有垂直晶体管和深沟槽电容器的存储器件。 该器件包括含有至少一个深沟槽和沉积在深沟槽的下部的电容器的衬底。 具有第一导电层和第二导电层的导电结构沉积在沟槽电容器上。 环形绝缘体沉积在侧壁上以及衬底和第一导电层之间。 第一导电层被环形绝缘体包围，并且第二导电层沉积在第一导电层和环形绝缘体上。 在深沟槽的侧壁的一侧上沉积第二导电层和深沟槽的衬底之间的扩散阻挡层。 TTO沉积在导电结构上。 控制门被存放在TTO上。