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公开(公告)号：US08222738B2
公开(公告)日：2012-07-17
申请号：US13212311
申请日：2011-08-18
IPC分类号： H01L21/56
CPC分类号： H01L23/49838 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2224/05001 , H01L2224/05026 , H01L2224/05568 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/81191 , H01L2224/814 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01019 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2924/014 , H01L2924/00012 , H01L2224/85 , H01L2224/83 , H01L2224/81 , H01L2224/05599 , H01L2224/05099
摘要： To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.
摘要翻译： 提供具有改善的可靠性的半导体器件。 半导体器件包括布线板，通过金凸块接合在布线板上的微计算机芯片倒装芯片，叠置在微计算机芯片上的第一存储芯片，用于将第一存储器芯片耦合到布线板的导线，用于将第一存储器芯片耦合到布线板的底部填充材料， 填充微型计算机芯片的倒装芯片连接部分，以及用树脂密封微型计算机芯片和第一存储器芯片的密封构件。 此外，在对底部填充材料充电时，对应于排气侧的芯片的角部的布线板的阻焊膜的第二开口部分的角部靠近微型计算机芯片，这可以提高润湿性和扩展 的第二开口部分的底部填充材料，从而减少了引线到第二开口部分的暴露，从而提高了半导体器件的可靠性。
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公开(公告)号：US08021932B2
公开(公告)日：2011-09-20
申请号：US12430277
申请日：2009-04-27
IPC分类号： H01L21/00
CPC分类号： H01L23/49838 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2224/05001 , H01L2224/05026 , H01L2224/05568 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/81191 , H01L2224/814 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01019 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2924/014 , H01L2924/00012 , H01L2224/85 , H01L2224/83 , H01L2224/81 , H01L2224/05599 , H01L2224/05099
摘要： To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.
摘要翻译： 提供具有改善的可靠性的半导体器件。 半导体器件包括布线板，通过金凸块接合在布线板上的微计算机芯片倒装芯片，叠置在微计算机芯片上的第一存储芯片，用于将第一存储器芯片耦合到布线板的导线，用于将第一存储器芯片耦合到布线板的底部填充材料， 填充微型计算机芯片的倒装芯片连接部分，以及用树脂密封微型计算机芯片和第一存储器芯片的密封构件。 此外，在对底部填充材料充电时，对应于排气侧的芯片的角部的布线板的阻焊膜的第二开口部分的角部靠近微型计算机芯片，这可以提高润湿性和扩展 的第二开口部分的底部填充材料，从而减少了引线到第二开口部分的暴露，从而提高了半导体器件的可靠性。
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公开(公告)号：US20090294945A1
公开(公告)日：2009-12-03
申请号：US12423826
申请日：2009-04-15
申请人： Mikako Okada , Toshikazu Ishikawa
发明人： Mikako Okada , Toshikazu Ishikawa
IPC分类号： H01L23/522 , H01L23/498 , H01L21/50
CPC分类号： H01L23/50 , H01L21/561 , H01L23/3128 , H01L23/49827 , H01L23/49838 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/28 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/056 , H01L2224/05624 , H01L2224/1134 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/29111 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48228 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/49171 , H01L2224/49431 , H01L2224/73204 , H01L2224/73265 , H01L2224/75 , H01L2224/75251 , H01L2224/81203 , H01L2224/81801 , H01L2224/83101 , H01L2224/83102 , H01L2224/83192 , H01L2224/83855 , H01L2224/85051 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85986 , H01L2224/92125 , H01L2224/92247 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10162 , H01L2924/12041 , H01L2924/14 , H01L2924/1517 , H01L2924/15183 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/30105 , H01L2924/3511 , H01L2224/83 , H01L2224/85 , H01L2224/81 , H01L2224/85186 , H01L2924/00012 , H01L2924/00 , H01L2224/13111 , H01L2924/3512 , H01L2224/45099 , H01L2224/4554
摘要： The mounting height of a semiconductor device is reduced. A wiring substrate has an upper surface with multiple bonding leads formed therein and a lower surface with multiple lands formed therein. This wiring substrate is a multilayer wiring substrate and multiple wiring layers and multiple insulating layers are alternately formed on the upper surface side and on the lower surface side of the core material of the wiring substrate. The bonding leads are formed of part of the uppermost wiring layer and the lands are formed of part of the lowermost wiring layer. The insulating layers include second insulating layers containing fiber and resin and third insulating layers smaller in fiber content than the second insulating layers. The second insulating layers are formed on the upper surface side and on the lower surface side of the core material. The third insulating layers are formed on the upper surface side and on the lower surface side of the core material with the second insulating layers in-between. The uppermost wiring layer and the lowermost wiring layer are formed over the third insulating layers.
摘要翻译： 降低了半导体器件的安装高度。 布线基板具有形成在其中的多个接合引线的上表面和形成有多个焊盘的下表面。 该布线基板是多层布线基板，并且在布线基板的芯材的上表面侧和下表面侧交替形成多个布线层和多个绝缘层。 接合引线由最上层布线层的一部分形成，焊盘由最下层布线层的一部分形成。 绝缘层包括含有纤维和树脂的第二绝缘层和比第二绝缘层小的纤维含量的第三绝缘层。 第二绝缘层形成在芯材的上表面侧和下表面侧上。 第三绝缘层形成在芯材的上表面侧和下表面侧，其间具有第二绝缘层。 最上面的布线层和最下面的布线层形成在第三绝缘层上。
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4.发明授权Semiconductor device having wiring substrate stacked on another wiring substrate 有权具有堆叠在另一布线基板上的布线基板的半导体器件公开(公告)号：US08159058B2
公开(公告)日：2012-04-17
申请号：US12203972
申请日：2008-09-04
申请人： Toshikazu Ishikawa , Mikako Okada
发明人： Toshikazu Ishikawa , Mikako Okada
IPC分类号： H01L23/02
CPC分类号： H01L21/50 , H01L22/32 , H01L23/498 , H01L24/73 , H01L25/105 , H01L25/18 , H01L2224/16225 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06575 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/00 , H01L2924/00012
摘要： Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.
摘要翻译： 促进半导体器件的小型化和高性能，其具有封装（POP）封装，其中多个半导体封装以多级堆叠。 用于确定微型计算机芯片和存储芯片的导通状态的质量的测试导电焊盘被布置在用于外部输入/输出的导电焊盘外部，从而将将微计算机芯片和存储器芯片耦合到测试的导线的路线 导电垫的长度减小。 此外，将微型计算机芯片和存储芯片耦合到测试导电焊盘的导线被耦合到两行的导电焊盘中的外排中的焊盘，以耦合到微计算机芯片。
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公开(公告)号：US08159057B2
公开(公告)日：2012-04-17
申请号：US12423826
申请日：2009-04-15
申请人： Mikako Okada , Toshikazu Ishikawa
发明人： Mikako Okada , Toshikazu Ishikawa
IPC分类号： H01L23/06
CPC分类号： H01L23/50 , H01L21/561 , H01L23/3128 , H01L23/49827 , H01L23/49838 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/28 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/056 , H01L2224/05624 , H01L2224/1134 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/29111 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48228 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/49171 , H01L2224/49431 , H01L2224/73204 , H01L2224/73265 , H01L2224/75 , H01L2224/75251 , H01L2224/81203 , H01L2224/81801 , H01L2224/83101 , H01L2224/83102 , H01L2224/83192 , H01L2224/83855 , H01L2224/85051 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85986 , H01L2224/92125 , H01L2224/92247 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10162 , H01L2924/12041 , H01L2924/14 , H01L2924/1517 , H01L2924/15183 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/30105 , H01L2924/3511 , H01L2224/83 , H01L2224/85 , H01L2224/81 , H01L2224/85186 , H01L2924/00012 , H01L2924/00 , H01L2224/13111 , H01L2924/3512 , H01L2224/45099 , H01L2224/4554
摘要： The mounting height of a semiconductor device is reduced. A wiring substrate has an upper surface with multiple bonding leads formed therein and a lower surface with multiple lands formed therein. This wiring substrate is a multilayer wiring substrate and multiple wiring layers and multiple insulating layers are alternately formed on the upper surface side and on the lower surface side of the core material of the wiring substrate. The bonding leads are formed of part of the uppermost wiring layer and the lands are formed of part of the lowermost wiring layer. The insulating layers include second insulating layers containing fiber and resin and third insulating layers smaller in fiber content than the second insulating layers. The second insulating layers are formed on the upper surface side and on the lower surface side of the core material. The third insulating layers are formed on the upper surface side and on the lower surface side of the core material with the second insulating layers in-between. The uppermost wiring layer and the lowermost wiring layer are formed over the third insulating layers.
摘要翻译： 降低了半导体器件的安装高度。 布线基板具有形成在其中的多个接合引线的上表面和形成有多个焊盘的下表面。 该布线基板是多层布线基板，并且在布线基板的芯材的上表面侧和下表面侧交替形成多个布线层和多个绝缘层。 接合引线由最上层布线层的一部分形成，焊盘由最下层布线层的一部分形成。 绝缘层包括含有纤维和树脂的第二绝缘层和比第二绝缘层小的纤维含量的第三绝缘层。 第二绝缘层形成在芯材的上表面侧和下表面侧上。 第三绝缘层形成在芯材的上表面侧和下表面侧，其间具有第二绝缘层。 最上面的布线层和最下面的布线层形成在第三绝缘层上。
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6.发明授权Semiconductor device with wiring substrate including lower conductive pads and testing conductive pads 有权具有布线基板的半导体器件包括下导电焊盘和测试导电焊盘公开(公告)号：US08698299B2
公开(公告)日：2014-04-15
申请号：US13409865
申请日：2012-03-01
申请人： Toshikazu Ishikawa , Mikako Okada
发明人： Toshikazu Ishikawa , Mikako Okada
IPC分类号： H01L23/02
CPC分类号： H01L21/50 , H01L22/32 , H01L23/498 , H01L24/73 , H01L25/105 , H01L25/18 , H01L2224/16225 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06575 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/00 , H01L2924/00012
摘要： Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.
摘要翻译： 促进半导体器件的小型化和高性能，其具有封装（POP）封装，其中多个半导体封装以多级堆叠。 用于确定微型计算机芯片和存储芯片的导通状态的质量的测试导电焊盘被布置在用于外部输入/输出的导电焊盘外部，从而将将微计算机芯片和存储器芯片耦合到测试的导线的路线 导电垫的长度减小。 此外，将微型计算机芯片和存储芯片耦合到测试导电焊盘的导线被耦合到两行的导电焊盘中的外排中的焊盘，以耦合到微计算机芯片。
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公开(公告)号：US08383456B2
公开(公告)日：2013-02-26
申请号：US13439992
申请日：2012-04-05
申请人： Mikako Okada , Toshikazu Ishikawa
发明人： Mikako Okada , Toshikazu Ishikawa
CPC分类号： H01L23/50 , H01L21/561 , H01L23/3128 , H01L23/49827 , H01L23/49838 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/28 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/056 , H01L2224/05624 , H01L2224/1134 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/29111 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48228 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/49171 , H01L2224/49431 , H01L2224/73204 , H01L2224/73265 , H01L2224/75 , H01L2224/75251 , H01L2224/81203 , H01L2224/81801 , H01L2224/83101 , H01L2224/83102 , H01L2224/83192 , H01L2224/83855 , H01L2224/85051 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85986 , H01L2224/92125 , H01L2224/92247 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10162 , H01L2924/12041 , H01L2924/14 , H01L2924/1517 , H01L2924/15183 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/30105 , H01L2924/3511 , H01L2224/83 , H01L2224/85 , H01L2224/81 , H01L2224/85186 , H01L2924/00012 , H01L2924/00 , H01L2224/13111 , H01L2924/3512 , H01L2224/45099 , H01L2224/4554
摘要： A multilayer wiring substrate has an upper surface with multiple bonding leads and a lower surface with multiple lands. Multiple wiring layers and insulating layers are alternately formed on the upper surface side and on the lower surface side of the core material of the wiring substrate. The bonding leads are formed of part of the uppermost wiring layer and the lands are formed of part of the lowermost wiring layer. The insulating layers include second insulating layers containing fiber and resin and third insulating layers smaller in fiber content than the second insulating layers. The second insulating layers are formed on the upper and lower surface sides of the core material. The third insulating layers are formed on the upper and lower surface sides of the core material with the second insulating layers in-between. The uppermost and lowermost wiring layers are formed over the third insulating layers.
摘要翻译： 多层布线基板具有多个接合引线的上表面和具有多个焊盘的下表面。 在布线基板的芯材的上表面侧和下表面侧交替形成多个布线层和绝缘层。 接合引线由最上层布线层的一部分形成，焊盘由最下层布线层的一部分形成。 绝缘层包括含有纤维和树脂的第二绝缘层和比第二绝缘层小的纤维含量的第三绝缘层。 第二绝缘层形成在芯材的上表面和下表面上。 第三绝缘层形成在芯材的上表面和下表面之间，其间具有第二绝缘层。 最上面和最下面的布线层形成在第三绝缘层上。
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