公开(公告)号：US20140027893A1

公开(公告)日：2014-01-30

申请号：US13771320

申请日：2013-02-20

Applicant: ZHEN DING TECHNOLOGY CO., LTD.

Inventor： E-TUNG CHOU ,  CHIH-JEN HSIAO

IPC: H05K1/11 ,  H01L23/495 ,  H05K1/09 ,  H01L23/00

CPC classification number: H05K1/112 ,  H01L21/48 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/4952 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/09 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A circuit board includes an insulation layer, an electrically conductive layer, and a solder mask layer. The insulation layer has a plurality of through holes passing through. The electrically conductive layer is formed on a surface of the insulation layer and covers the through holes. The electrically conductive layer has a plurality of portions exposed in the through holes to serve as a plurality of first conductive pads. The solder mask layer covers the electrically conductive layer and defines a plurality of openings to expose parts of the electrically conductive layer. Parts of the electrically conductive layer are exposed to the solder mask layer to serve as a plurality of second conductive pads. The second conductive pads are electrically connected to the first conductive pads respectively. This disclosure further relates to a chip package and a method of manufacturing the same.

Abstract translation: 电路板包括绝缘层，导电层和焊料掩模层。 绝缘层具有穿过的多个通孔。 导电层形成在绝缘层的表面上并覆盖通孔。 导电层具有暴露在通孔中的多个部分以用作多个第一导电焊盘。 焊接掩模层覆盖导电层并且限定多个开口以暴露部分导电层。 导电层的一部分暴露于焊料掩模层以用作多个第二导电焊盘。 第二导电焊盘分别电连接到第一导电焊盘。 本公开还涉及芯片封装及其制造方法。

公开(公告)号：US20150014849A1

公开(公告)日：2015-01-15

申请号：US14331330

申请日：2014-07-15

Applicant: Zhen Ding Technology Co., Ltd.

Inventor： YONG HA WOO ,  E-TUNG CHOU ,  WEN-LUN LO

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/24 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2224/24247 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H05K1/185 ,  H05K3/0097 ,  H05K3/4682 ,  H05K2203/1536 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A coreless package structure and a method for manufacturing same includes the steps of providing a supporting substrate comprising an etching resist layer and a copper foil. A groove is defined in the copper foil and a plurality of contact pads are formed on the surface of the copper foil. A chip including a plurality of electrode pads is received in the groove and a packaging layer is formed on a side of the copper foil. An insulating layer and a conductive pattern layer are formed on the packaging layer in that order, the conductive pattern layer being electrically connected to the contact pads and the electrode pads by a plurality of conductive bumps. Finally, the etching resist layer and the copper foil are removed to obtain a coreless package structure.

Abstract translation: 无芯封装结构及其制造方法包括提供包括抗蚀剂层和铜箔的支撑基板的步骤。 在铜箔中限定有凹槽，并且在铜箔的表面上形成多个接触垫。 包含多个电极焊盘的芯片被容纳在槽中，并且在铜箔的一侧上形成封装层。 绝缘层和导电图案层依次形成在封装层上，导电图案层通过多个导电凸块与接触焊盘和电极焊盘电连接。 最后，除去抗蚀剂层和铜箔，得到无芯封装结构。

公开(公告)号：US20140185259A1

公开(公告)日：2014-07-03

申请号：US14097251

申请日：2013-12-05

Applicant: ZHEN DING TECHNOLOGY CO., LTD.

Inventor： YONG HA WOO ,  E-TUNG CHOU ,  WEN-LUN LO

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/00 ,  H05K1/09

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/09 ,  H01L2224/08238 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/15738 ,  H01L2924/181 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0017 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/0347 ,  H05K2201/0379 ,  H05K2201/09836 ,  H05K2201/10674 ,  H05K2203/0384 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts are larger than that of each of the first conductive posts.

Abstract translation: 封装基板包括电路板，多个第一导电柱和多个第二导电柱。 电路板包括形成在第一基底的第一表面上的第一基底和第一导电图案层。 第一导电柱从第一导电图案层延伸并电连接到第一导电图案层。 第二导电柱从第一导电图案层延伸并与之电连接。 每个第二导电柱的高度大于每个第一导电柱的高度。

公开(公告)号：US20140085833A1

公开(公告)日：2014-03-27

申请号：US14029735

申请日：2013-09-17

Applicant: Zhen Ding Technology Co., Ltd.

Inventor： SHIH-PING HSU ,  E-TUNG CHOU ,  CHIH-JEN HSIAO

IPC: H05K1/18 ,  H05K1/00 ,  H05K3/42 ,  H05K3/46 ,  H05K3/28

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/00 ,  H05K3/0097 ,  H05K3/281 ,  H05K3/421 ,  H05K3/4652 ,  H05K3/4682 ,  Y10T29/49162 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip packaging substrate includes a dielectric layer, a first inner wiring layer embedded in the dielectric layer, an outer wiring layer, and many conductive connection points. The outer wiring layer is formed at one side of the dielectric layer, and is electrically connected to the first inner wiring layer through many first conductive vias in the dielectric layer. The conductive connection points are formed at the other side of the dielectric layer, and are electrically connected to the first inner wiring layer through many second conductive vias in the dielectric layer.

Abstract translation: 芯片封装基板包括电介质层，埋在电介质层中的第一内部布线层，外部布线层以及许多导电连接点。 外部布线层形成在电介质层的一侧，并且通过电介质层中的许多第一导电通孔与第一内部布线层电连接。 导电连接点形成在电介质层的另一侧，并通过电介质层中的许多第二导电通孔与第一内部布线层电连接。

公开(公告)号：US20140036465A1

公开(公告)日：2014-02-06

申请号：US13863400

申请日：2013-04-16

Applicant: ZHEN DING TECHNOLOGY CO., LTD.

Inventor： CHU-CHIN HU ,  SHIH-PING HSU ,  E-TUNG CHOU

IPC: H05K1/18 ,  H05K3/40

CPC classification number: H05K1/181 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K3/0097 ,  H05K3/4038 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A packaging substrate includes a copper foil substrate, a sputtering copper layer, a dielectric layer, a plurality of electrically conductive connection points, and an electrically conductive pattern layer. The sputtering copper layer is formed on the copper foil substrate. The electrically conductive connection points are formed on a surface of the sputtering copper layer, which is away from the copper foil substrate. The dielectric layer is sandwiched between the electrically conductive pattern layer and the sputtering copper layer. A plurality of first blind via are formed in the first dielectric layer. The electrically conductive pattern layer includes a plurality of electrically conductive traces and a plurality of connection pads. Each electrically conductive connection point is electrically connected to the electrically conductive trace by the first blind via.

Abstract translation: 封装基板包括铜箔基板，溅射铜层，电介质层，多个导电连接点以及导电图案层。 在铜箔基板上形成溅射铜层。 导电连接点形成在溅射铜层的远离铜箔衬底的表面上。 电介质层夹在导电图案层和溅射铜层之间。 多个第一通孔形成在第一电介质层中。 导电图案层包括多个导电迹线和多个连接焊盘。 每个导电连接点通过第一盲通孔电连接到导电迹线。

公开(公告)号：US20140117553A1

公开(公告)日：2014-05-01

申请号：US13968409

申请日：2013-08-15

Applicant: Zhen Ding Technology Co., Ltd.

Inventor： YONG HA WOO ,  E-TUNG CHOU ,  WEN-LUN LO

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A packaging substrate includes a base layer, a first wiring layer, a second wiring layer, a first solder mask layer, a second solder mask layer and copper portions. The first second wiring layers are arranged on opposite sides of the base layer. The first solder mask layer covers the first wiring layer, and defines plenty of first openings. The first wiring layer exposed through the first openings serves as first contact pads. The second solder mask layer covers the second wiring layer. The second solder mask layer defines plenty of second openings. The second wiring layer exposed through the second openings serves as second contact pads. The copper portions are formed on the second contact pads. The copper portions protrude beyond the second solder mask layer. This disclosure further relates to a method of manufacturing the packaging substrate and a chip packaging body.

Abstract translation: 封装基板包括基底层，第一布线层，第二布线层，第一焊料掩模层，第二焊接掩模层和铜部分。 第一第二布线层布置在基层的相对侧上。 第一焊接掩模层覆盖第一布线层，并且限定了大量的第一开口。 通过第一开口露出的第一布线层用作第一接触垫。 第二焊料掩模层覆盖第二布线层。 第二焊接掩模层限定了大量的第二开口。 通过第二开口暴露的第二布线层用作第二接触垫。 铜部分形成在第二接触焊盘上。 铜部分突出超过第二焊接掩模层。 本公开还涉及制造封装基板和芯片封装体的方法。

公开(公告)号：US20140078706A1

公开(公告)日：2014-03-20

申请号：US13971854

申请日：2013-08-21

Applicant: ZHEN DING TECHNOLOGY CO., LTD.

Inventor： CHU-CHIN HU ,  SHIH-PING HSU ,  E-TUNG CHOU ,  CHIH-JEN HSIAO

IPC: H05K1/11

CPC classification number: H05K1/112 ,  H01L21/4853 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73104 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A packaging substrate includes a supporting sheet, a copper foil, a number of connecting pads, a number of solder balls, a resin layer, a wiring layer and a solder mask layer. The copper foil is attached on a surface of the supporting sheet through an adhesive sheet. The connecting pads are formed on the copper foil. The solder balls are formed on the connecting pads. The resin layer infills the gaps between the solder balls. The wiring layer is formed on the resin layer and the solder balls. Terminal portions of the solder balls facing away from the connecting pads are electrically connected to the wiring layer. The solder mask layer is formed on the wiring layer. The solder mask layer defines a number of openings exposing portions of the wiring layer. The portions of the wiring layer exposed through the openings serve as contact pads.

Abstract translation: 包装基板包括支撑片，铜箔，多个连接焊盘，多个焊球，树脂层，布线层和焊料掩模层。 铜箔通过粘合片附着在支撑片材的表面上。 连接焊盘形成在铜箔上。 焊球形成在连接焊盘上。 树脂层填充焊球之间的间隙。 布线层形成在树脂层和焊球上。 焊料球的背离连接焊盘的端子部分电连接到布线层。 在布线层上形成焊料掩模层。 焊接掩模层限定暴露部分布线层的多个开口。 通过开口露出的布线层的部分作为接触垫。