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    SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON
    2.
    发明申请
    SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON 有权
    使用POLYSILICON的TRENCH-DMOS器件的源和体接触结构

    公开(公告)号：US20140225188A1

    公开(公告)日：2014-08-14

    申请号：US14256843

    申请日：2014-04-18

    申请人： Alpha & Omega Semiconductor, LTD

    发明人： François Hébert ,  Anup Bhalla

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7813 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734

    摘要： A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译： 半导体器件包括栅极电极，设置在栅电极旁边的顶部源极区域，设置在栅极电极底部的漏极区域，设置在源极区域和栅极电极顶部的氧化物以及掺杂多晶硅间隔物 沿着源区域的侧壁和氧化物的侧壁设置。 还公开了制造这种装置的方法。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

    Source and body contact structure for trench-DMOS devices using polysilicon
    3.
    发明授权
    Source and body contact structure for trench-DMOS devices using polysilicon 有权
    使用多晶硅的沟槽DMOS器件的源和体接触结构

    公开(公告)号：US08703563B2

    公开(公告)日：2014-04-22

    申请号：US13559490

    申请日：2012-07-26

    申请人： François Hébert ,  Anup Bhalla

    发明人： François Hébert ,  Anup Bhalla

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734

    摘要： A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译： 半导体器件包括栅极电极，设置在栅电极旁边的顶部源极区域，设置在栅极电极底部的漏极区域，设置在源极区域和栅极电极顶部的氧化物以及掺杂多晶硅间隔物 沿着源区域的侧壁和氧化物的侧壁设置。 还公开了制造这种装置的方法。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

    Layouts for multiple-stage ESD protection circuits for integrating with semiconductor power device
    6.
    发明授权
    Layouts for multiple-stage ESD protection circuits for integrating with semiconductor power device 有权
    用于与半导体功率器件集成的多级ESD保护电路布局

    公开(公告)号：US08053808B2

    公开(公告)日：2011-11-08

    申请号：US11804906

    申请日：2007-05-21

    申请人： Yi Su ,  Anup Bhalla ,  Daniel Ng ,  Wei Wang ,  Ji Pan

    发明人： Yi Su ,  Anup Bhalla ,  Daniel Ng ,  Wei Wang ,  Ji Pan

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7811 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor power device supported on a semiconductor substrate includes a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a source metal connected to the source region, and a gate metal configured as a metal stripe surrounding a peripheral region of the substrate connected to a gate pad wherein the gate metal and the gate pad are separated from the source metal by a metal gap. The semiconductor power device further includes an ESD protection circuit includes a plurality of doped polysilicon regions of opposite conductivity types constituting ESD diodes extending across the metal gap and connected between the gate metal and the source metal on the peripheral region of the substrate.

    摘要翻译： 支撑在半导体衬底上的半导体功率器件包括多个晶体管单元，每个晶体管单元具有源极和漏极，栅极用于控制在源极和漏极之间传输的电流。 半导体还包括连接到源极区的源极金属和栅极金属，该栅极金属被配置为围绕连接到栅极焊盘的衬底的外围区域的金属条，其中栅极金属和栅极焊盘与源极金属分离 金属间隙。 半导体功率器件还包括ESD保护电路，其包括构成ESD保护二极管的相反导电类型的多个掺杂多晶硅区域，该ESD二极管延伸穿过金属间隙并连接在栅极金属与源极金属之间。

    Inverted-trench grounded-source FET structure with trenched source body short electrode
    8.
    发明授权
    Inverted-trench grounded-source FET structure with trenched source body short electrode 有权
    反沟槽接地源FET结构，具有沟槽源体短路电极

    公开(公告)号：US08008716B2

    公开(公告)日：2011-08-30

    申请号：US11522669

    申请日：2006-09-17

    申请人： Sik K Lui ,  François Hébert ,  Anup Bhalla

    发明人： Sik K Lui ,  François Hébert ,  Anup Bhalla

    IPC分类号： H01L29/66

    CPC分类号： H01L29/781 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

    摘要： This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.

    摘要翻译： 本发明公开了底源横向扩散MOS（BS-LDMOS）器件。 器件具有在半导体衬底的顶表面附近的漏区附近设置的源极区域，该半导体衬底在源极区域和漏极区域之间支撑栅极。 BS-LDMOS器件还具有一个组合的沉降通道区域，该半导体衬底的深度完全位于靠近顶表面的源极区域附近设置的体区域之下，其中组合沉降通道区域用作掩埋源体 用于将主体区域和源区域电连接到用作源电极的衬底的底部。 漂移区域设置在栅极下方的顶表面附近并且远离源极区域并且延伸到并包围漏极区域。 在漂移区域下方延伸的组合沉降通道区域和具有与掺杂剂 - 导电性相反并补偿漂移区域以减少源极 - 漏极电容的组合沉降沟道区域。

    Electrostatic discharge (ESD) protection applying high voltage lightly doped drain (LDD) CMOS technologies
    9.
    发明授权
    Electrostatic discharge (ESD) protection applying high voltage lightly doped drain (LDD) CMOS technologies 有权
    使用高电压轻掺杂漏极（LDD）CMOS技术的静电放电（ESD）保护

    公开(公告)号：US07919817B2

    公开(公告)日：2011-04-05

    申请号：US12152805

    申请日：2008-05-16

    申请人： Shekar Mallikarjunaswamy

    发明人： Shekar Mallikarjunaswamy

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0251

    摘要： An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied. In an exemplary embodiment, the dopant profile of the PG region includes two dopant implant profiles that include a shallow implant profile with a higher dopant concentration and a deep implant profile with a lower dopant concentration.

    摘要翻译： 静电放电（ESD）保护电路包括触发二极管，其包括P级（PG）区域和N阱之间的连接点。 PG区域具有等效于具有由V表示的击穿电压的PMOS晶体管的P漏极掺杂物轮廓的掺杂物轮廓，由此施加大于击穿电压V的电压时用于传导电流的触发二极管。 在示例性实施例中，PG区域的掺杂物分布包括两个掺杂剂注入分布，其包括具有较高掺杂剂浓度的较浅注入分布和具有较低掺杂浓度的深注入分布。

    Methods of achieving linear capacitance in symmetrical and asymmetrical EMI filters with TVS
    10.
    发明授权
    Methods of achieving linear capacitance in symmetrical and asymmetrical EMI filters with TVS 有权
    在TVS对称和不对称EMI滤波器中实现线性电容的方法

    公开(公告)号：US07863995B2

    公开(公告)日：2011-01-04

    申请号：US12080104

    申请日：2008-04-01

    申请人： Moses Ho ,  Madhur Bobde ,  Mike Chang ,  Limin Weng

    发明人： Moses Ho ,  Madhur Bobde ,  Mike Chang ,  Limin Weng

    IPC分类号： H04B3/28 ,  H01L25/00

    CPC分类号： H01L27/0676 ,  H01L23/552 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A transient voltage suppressing (TVS) circuit with uni-directional blocking and symmetric bi-directional blocking capabilities integrated with an electromagnetic interference (EMI) filter supported on a semiconductor substrate of a first conductivity type. The TVS circuit integrated with the EMI filter further includes a ground terminal disposed on the surface for the symmetric bi-directional blocking structure and at the bottom of the semiconductor substrate for the uni-directional blocking structure and an input and an output terminal disposed on a top surface with at least a Zener diode and a plurality of capacitors disposed in the semiconductor substrate to couple the ground terminal to the input and output terminals with a direct capacitive coupling without an intermediate floating body region.

    摘要翻译： 具有与第一导电类型的半导体衬底上支持的电磁干扰（EMI）滤波器集成的具有单向阻塞和对称双向阻塞能力的瞬态电压抑制（TVS）电路。 与EMI滤波器集成的TVS电路还包括设置在用于对称双向阻塞结构的表面上的接地端子和用于单向阻塞结构的半导体衬底的底部以及设置在单向阻断结构上的输入和输出端子 具有至少齐纳二极管的顶表面和设置在半导体衬底中的多个电容器，以将接地端子连接到具有直接电容耦合而不具有中间浮体区域的输入和输出端子。