公开(公告)号：US08278200B2

公开(公告)日：2012-10-02

申请号：US13012043

申请日：2011-01-24

Applicant: Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

Inventor： Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

IPC: H01L21/20

CPC classification number: H01L21/28518

Abstract: In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

Abstract translation: 在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层， 第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。

公开(公告)号：US20190051563A1

公开(公告)日：2019-02-14

申请号：US15676005

申请日：2017-08-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Ruilong Xie ,  Min Gyu Sung

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor patterned in a self-aligned process. A plurality of fins is formed. A gate structure is formed on at least a first side and a second side of a lower portion of each fin. A spacer is formed on at least a first side and a second side of an upper portion of each fin. At least one layer is formed above the substrate and between the fins. An opening is formed in the at least one layer between the fins by an etching process. The spacer protects the gate structure during the etching process.

公开(公告)号：US20180358272A1

公开(公告)日：2018-12-13

申请号：US15622061

申请日：2017-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mitsuhiro Togo ,  Ram Asra ,  Xing Zhang ,  Palanivel Balasubramaniam

IPC: H01L21/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L22/20 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/42376

Abstract: At least one method, apparatus and system are disclosed for controlling threshold voltage values for a plurality of transistor devices. Determine a first threshold voltage of a first transistor gate comprising a first gate channel having a first length. Determine a second length of a second gate channel of a second transistor gate. Determining a process adjustment of the second gate based on the second length for providing a second threshold voltage of the second transistor gate. The second threshold voltage is within a predetermined range of the first threshold voltage. Provide data relating to process adjustment to a process controller for performing the process adjustment.

公开(公告)号：US20190242927A1

公开(公告)日：2019-08-08

申请号：US15890270

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ronald A. Feroli ,  John Cassels ,  Matthew F. Stanton

IPC: G01R1/073 ,  G01R31/26

Abstract: A continuity testing and cleaning fixture includes a continuity test area disposed on a portion of a first surface of the fixture, wherein the continuity test area comprises an upper region comprising at least 99.99 wt % tungsten. The continuity testing and cleaning fixture may be used in a method involving contacting at least two conductive elements of a probe card with a continuity test area of a continuity testing and cleaning fixture, wherein the continuity test area comprises an upper region comprising at least 99.99 wt % tungsten; determining an electrical resistance between the at least two conductive elements; and cleaning the at least two conductive elements with at least one cleaning zone of the continuity testing and cleaning fixture in response to determining the electrical resistance to be above a first threshold.

公开(公告)号：US09190303B2

公开(公告)日：2015-11-17

申请号：US14716236

申请日：2015-05-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Douglas C. La Tulipe, Jr. ,  Wei Lin ,  Spyridon Skordas ,  Kevin R. Winstel

IPC: G01R31/26 ,  G06F19/00 ,  H01L21/67 ,  H01L23/00 ,  H01L21/324

CPC classification number: H01L21/67259 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/324 ,  H01L22/12 ,  H01L22/20 ,  H01L24/83 ,  H01L24/94

Abstract: A bonding layer of a first wafer article is thermally treated and a bonding layer of a second wafer article is thermally treated in accordance with first and second process parameters, respectively prior to bonding the first wafer article with the second wafer article. First and second grid distortion in the first and second wafer articles is measured and a difference is determined between the first and second grid distortions. A prediction is made for maintaining the difference within a prescribed tolerance. At least one of the first process parameters and the second process parameters is conditionally varied in accordance with the prediction. The thermal treating of the first and second wafer articles can then be performed with respect to another pair of the first and second wafer articles prior to bonding to one another through their respective bonding layers.

Abstract translation: 对第一晶片制品的接合层进行热处理，并且在将第一晶片制品与第二晶片制品接合之前，分别根据第一和第二工艺参数对第二晶片制品的粘结层进行热处理。 测量第一和第二晶片制品中的第一和第二网格变形，并且在第一和第二格栅失真之间确定差异。 进行预测以将差异保持在规定的公差内。 第一处理参数和第二处理参数中的至少一个根据预测有条件地变化。 然后可以在通过其各自的结合层彼此粘合之前相对于另一对第一和第二晶片制品执行第一和第二晶片制品的热处理。

公开(公告)号：US20190081175A1

公开(公告)日：2019-03-14

申请号：US15702278

申请日：2017-09-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  Hong Yu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein involves forming a sigma shaped source/drain lattice. A fin is formed on a semiconductor substrate. A gate region is formed over the fin. In a source region and a drain region adjacent bottom portions of the fin, a first recess cavity is formed in the source region, and a second recess cavity is formed in the drain region. The first and second recess cavities comprise sidewalls formed in an angle relative to a vertical axis. Portions of the first and second recess cavities extend below the fin. In the first recess cavity, a first rare earth oxide layer is formed, and in the second recess cavity, a second rare earth oxide layer is formed.

公开(公告)号：US20180012798A1

公开(公告)日：2018-01-11

申请号：US15689413

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre LABONTE ,  Ruilong XIE ,  Xunyuan ZHANG

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L23/535 ,  H01L23/522 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/823431 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a high-k dielectric liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the cap. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core and liner at an intermediate portion of the CB trench. The core is selectively etched relative to the liner to extend the CB trench to a bottom at the gate metal. The CB trench is metalized to form a CB contact.

公开(公告)号：US20180012647A1

公开(公告)日：2018-01-11

申请号：US15711714

申请日：2017-09-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hema Ramamurthy ,  Sanjay Parihar ,  Jongsin Yun

IPC: G11C11/412 ,  G11C11/419 ,  H01L27/11 ,  H01L27/12

CPC classification number: G11C11/412 ,  G11C11/419 ,  H01L27/1104 ,  H01L27/1112 ,  H01L27/1203

Abstract: At least one method, apparatus and system disclosed involves a memory device having a memory cell comprising NMOS only transistors. An SRAM bit cell comprises a first pass gate (PG) NMOS transistor coupled to a first bit line signal and a word line signal; a second PG NMOS transistor coupled to a second bit line signal and the word line signal; a first pull down (PD) NMOS transistor operatively coupled to the first PG NMOS transistor; a second PD NMOS transistor operatively coupled to the second PG NMOS transistor; a first pull up (PU) NMOS transistor operatively coupled to the first PD NMOS transistor; and a second PU NMOS transistor operatively coupled to the second PD NMOS transistor. Each of the back gates of the first and second PU NMOS transistors are coupled to a predetermined voltage signal for biasing the first and second PU NMOS transistors.

公开(公告)号：US09780031B2

公开(公告)日：2017-10-03

申请号：US14477535

申请日：2014-09-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Cathryn J. Christiansen ,  Roger A. Dufresne ,  Charles W. Griffin

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Wiring structures with dummy metal features and methods of manufacture are disclosed. A structure includes a metal wiring structure, and dummy metal features in electrical and direct physical contact with the metal wiring structure in a same plane as the metal wiring structure. The dummy metal features do not change a resistance of the metal wiring structure and are remote from other structures.

公开(公告)号：US20190097015A1

公开(公告)日：2019-03-28

申请号：US15716287

申请日：2017-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Daniel Jaeger ,  Haigou Huang ,  Veeraraghavan Basker ,  Christopher Nassar ,  Jinsheng Gao ,  Michael Aquilino

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/321

CPC classification number: H01L29/4933 ,  H01L21/02425 ,  H01L21/2257 ,  H01L21/28052 ,  H01L21/3212 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.