公开(公告)号：US09165872B2

公开(公告)日：2015-10-20

申请号：US14523066

申请日：2014-10-24

Applicant: SFI Electronics Technology Inc.

Inventor： Ching-Hohn Lien ,  Xing-Xiang Huang ,  Hsing-Tsai Huang ,  Hong-Zong Xu

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/28 ,  H01L21/44 ,  H01L21/48 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49555 ,  H01L23/49562 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/2732 ,  H01L2224/2741 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29369 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/9221 ,  H01L2224/97 ,  H01L2924/00015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12 ,  H01L2924/1203 ,  H01L2924/12032 ,  H01L2924/12035 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/48

Abstract: A novel chip scale diode package due to no containing outer lead pins is miniaturized like a chip scale appearance to promote dimensional accuracy so that the diode package is so suitably produced by automation equipment to get automated mass production; the produced diode package may contain one or more diode chips to increase versatile functions more useful in applications, such as produced as a SMT diode package or an array-type SMT diode, and the present diode package due to made of no lead-containing material conforms to requirements for environmental protection.

Abstract translation: 由于不含外部引脚引脚的新颖的芯片尺寸二极管封装小型化，像芯片尺寸外观，以提高尺寸精度，使得二极管封装由自动化设备适当地生产以获得自动批量生产; 所生成的二极管封装可以包含一个或多个二极管芯片，以增加在应用中更有用的通用功能，例如作为SMT二极管封装或阵列型SMT二极管制造的，以及由于不含含铅材料制成的本二极管封装 符合环保要求。

公开(公告)号：US09947444B1

公开(公告)日：2018-04-17

申请号：US15709606

申请日：2017-09-20

Applicant: SFI Electronics Technology Inc.

Inventor： Ching-Hohn Lien ,  Jie-An Zhu ,  Zhi-Xian Xu ,  Ting-Yi Fang ,  Hong-Zong Xu

IPC: H01C7/10 ,  H01C17/06 ,  H01C7/102 ,  H01C17/28 ,  H01C1/14

CPC classification number: H01C17/06 ,  H01C1/14 ,  H01C7/1006 ,  H01C7/102 ,  H01C7/112 ,  H01C7/18 ,  H01C17/065 ,  H01C17/06546 ,  H01C17/281

Abstract: A process for producing a multilayer varistor (MLV) if remained its size unchanged as prior arts is favorable to outstandingly increase overall current-carrying area and improve the performance of final produced MLV; and the MLV has laminated a lower cap, an inner-electrode stack formed from piling up several inner-electrode gaps (g), and an upper cap into a unity, and at least satisfies the condition that the lower cap and the upper cap has a thickness smaller than a thickness of the inner-electrode gap (g), but equal to or greater than 0.1 times of the thickness of the inner-electrode gap (g).

公开(公告)号：US09443825B2

公开(公告)日：2016-09-13

申请号：US15018896

申请日：2016-02-09

Applicant: SFI Electronics Technology Inc.

Inventor： Ching-Hohn Lien ,  Xing-Xiang Huang ,  Hsing-Tsai Huang ,  Jie-An Zhu ,  Hong-Zong Xu ,  Yi-Wei Chen ,  Jung-Chun Chiang

IPC: H01L21/48 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29369 ,  H01L2224/32145 ,  H01L2224/32227 ,  H01L2224/33181 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2924/186 ,  H01L2224/83 ,  H01L2924/00014

Abstract: A surface-mount device (SMD) uses no conventional lead frame and contains a multi-function die module formed from either a single die or two or more dies electrically connected in series, in parallel, or in any combination of series and parallel, to provide such a SMD having one or more different functions including wave filtration, rectification, surge protection, sensing, current limiting, voltage regulation or prevention from voltage backflow, as compared to the prior art, the SMD disclosed is formed from fewer components, is simpler to manufacture and more effectively reduce layout wire length and noise.

Abstract translation: 表面安装器件（SMD）不使用常规的引线框架，并且包含由单个管芯或两个或更多个串联，并联或串联和并联的任何组合电连接的模具形成的多功能模具模块， 与现有技术相比，提供这样的SMD具有一个或多个不同的功能，包括波滤波，整流，浪涌保护，感测，限流，电压调节或防止电压回流，所公开的SMD由较少的部件形成，更简单 制造更有效地减少布线长度和噪声。

公开(公告)号：US20160035697A1

公开(公告)日：2016-02-04

申请号：US14881558

申请日：2015-10-13

Applicant: SFI Electronics Technology Inc.

Inventor： Ching-Hohn LIEN ,  Xing- Xiang HUANG ,  Hsing-Tsai HUANG ,  Hong-Zong XU ,  Yi-Wei CHEN

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48

CPC classification number: H01L24/97 ,  H01L21/4853 ,  H01L21/4867 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L21/7813 ,  H01L23/02 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/49805 ,  H01L23/49833 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L25/0652 ,  H01L29/861 ,  H01L2224/06181 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29369 ,  H01L2224/32168 ,  H01L2224/32227 ,  H01L2224/33181 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/1203 ,  H01L2924/12032 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/15798 ,  H01L2924/181 ,  H01L2924/186 ,  H05K1/117 ,  H05K1/144 ,  H05K1/145 ,  H05K3/403 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/83

Abstract: A process for producing a miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from the process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect.

Abstract translation: 制造小型化的SMD二极管封装的方法包括使用在封装期间使用电路板代替传统引线框架的底表面具有正极和负极的二极管芯片，并且使用电荷耦合器件（CCD）图像配准 技术进行芯片焊接; 由于使用电路板代替常规使用的引线框架，从制造过程中带来的有益优点包括简化制造工艺并降低制造成本，提高生产小型化SMD二极管封装的精度和精度，并确保 生产的小型SMD二极管封装具有优异的二极管特性，无失真或缺陷。

公开(公告)号：US20080191834A1

公开(公告)日：2008-08-14

申请号：US11704987

申请日：2007-02-12

Applicant: Ching-Hohn Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang ,  Xing-Guang Huang ,  Wei-Cheng Lien

Inventor： Ching-Hohn Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang ,  Xing-Guang Huang ,  Wei-Cheng Lien

IPC: H01C7/12 ,  C03C11/00

CPC classification number: H01C7/105 ,  B82Y30/00 ,  C03C14/006 ,  C03C2214/05 ,  C03C2214/08 ,  C03C2214/16 ,  C04B35/453 ,  C04B35/46 ,  C04B35/4682 ,  C04B35/47 ,  C04B35/565 ,  C04B35/624 ,  C04B35/62805 ,  C04B35/62807 ,  C04B35/62886 ,  C04B2235/3275 ,  C04B2235/3284 ,  C04B2235/3298 ,  C04B2235/36 ,  C04B2235/405 ,  C04B2235/408 ,  C04B2235/5436 ,  C04B2235/5445 ,  C04B2235/5454 ,  C04B2235/6025 ,  H01C7/12

Abstract: A low-capacitance multilayer chip varistor has capacitance lower than 0.5 pF at 1 MHz and has a characteristic of resisting more than thousands of times of 8 KV electrostatic shock, which comprises a ceramic main body, outer electrodes disposed at two ends of the ceramic main body and inner electrodes disposed therein; the ceramic main body comprises inorganic glass of 3˜50 wt % and semi-conductive or conductive particles of 50˜97 wt % with particle size of more than 0.1 μm, and a layer of inorganic glass film covers the surface of semi-conductive or conductive particles, wherein the inorganic glass film contains semi-conductive or conductive particles of submicron or nanometer which is smaller than 1 micron, and the quantity contained of semi-conductive or conductive particles is less than 20 wt % of that of inorganic glass.

Abstract translation: 低容量多层片式压敏电阻在1MHz时的电容低于0.5pF，具有耐8千伏静电电击的数千倍的特性，其中包括一陶瓷主体，外电极位于陶瓷主体的两端 主体和内部电极; 陶瓷主体包括3〜50重量％的无机玻璃和50〜97重量％的粒径大于0.1微米的半导体或导电颗粒，无机玻璃膜层覆盖半导体或 导电颗粒，其中无机玻璃膜含有小于1微米的亚微米或纳米的半导电或导电颗粒，并且半导体或导电颗粒所含的量小于无机玻璃的20重量％。

公开(公告)号：US09691736B2

公开(公告)日：2017-06-27

申请号：US14881558

申请日：2015-10-13

Applicant: SFI Electronics Technology Inc.

Inventor： Ching-Hohn Lien ,  Xing-Xiang Huang ,  Hsing-Tsai Huang ,  Hong-Zong Xu ,  Yi-Wei Chen

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/02 ,  H01L23/15 ,  H01L23/31 ,  H01L29/861 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/14 ,  H05K3/40 ,  H01L25/065

CPC classification number: H01L24/97 ,  H01L21/4853 ,  H01L21/4867 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L21/7813 ,  H01L23/02 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/49805 ,  H01L23/49833 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L25/0652 ,  H01L29/861 ,  H01L2224/06181 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29369 ,  H01L2224/32168 ,  H01L2224/32227 ,  H01L2224/33181 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/1203 ,  H01L2924/12032 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/15798 ,  H01L2924/181 ,  H01L2924/186 ,  H05K1/117 ,  H05K1/144 ,  H05K1/145 ,  H05K3/403 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/83

Abstract: A process for producing a miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from the process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect.

公开(公告)号：US09691735B2

公开(公告)日：2017-06-27

申请号：US14585857

申请日：2014-12-30

Applicant: SFI Electronics Technology Inc.

Inventor： Ching-Hohn Lien ,  Xing-Xiang Huang ,  Hsing-Tsai Huang ,  Hong-Zong Xu ,  Yi-Wei Chen

IPC: H01L27/15 ,  H01L29/267 ,  H01L31/12 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/02 ,  H01L23/15 ,  H01L23/31 ,  H01L29/861 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/14 ,  H05K3/40 ,  H01L25/065

CPC classification number: H01L24/97 ,  H01L21/4853 ,  H01L21/4867 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L21/7813 ,  H01L23/02 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/49805 ,  H01L23/49833 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L25/0652 ,  H01L29/861 ,  H01L2224/06181 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29369 ,  H01L2224/32168 ,  H01L2224/32227 ,  H01L2224/33181 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/1203 ,  H01L2924/12032 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/15798 ,  H01L2924/181 ,  H01L2924/186 ,  H05K1/117 ,  H05K1/144 ,  H05K1/145 ,  H05K3/403 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/83

Abstract: A miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from a process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect.

公开(公告)号：US08363382B2

公开(公告)日：2013-01-29

申请号：US13024470

申请日：2011-02-10

Applicant: Ching-Hohn Lien ,  Hong-Zong Xu

Inventor： Ching-Hohn Lien ,  Hong-Zong Xu

IPC: H01G4/005

CPC classification number: H01G4/005 ,  H01G4/30 ,  Y10T428/12056

Abstract: A multilayer ceramic device comprises a laminated ceramic body having opposite end surfaces, a pair of conductive electrodes each respectively attached to one end surface of the laminated ceramic body and a plurality of alternately staggered internal electrodes within the laminated ceramic body configured in an alternating manner and each electrically connected to the corresponding conductive electrodes respectively; each conductive electrodes of the multilayer ceramic device is further covered with a solder paste layer so that the multilayer ceramic device is thus made without any plating step and no need of treating waste liquid nickel or waste liquid tin as well as no problem of environmental pollution caused by plating solution, thereby lowering manufacturing costs and reducing processing time.

Abstract translation: 多层陶瓷器件包括具有相对端面的层叠陶瓷体，分别安装在层叠陶瓷体的一个端面上的一对导电电极和层叠陶瓷体内的多个交错交错的内部电极，其以交替的方式配置和 各自电连接到相应的导电电极; 多层陶瓷器件的每个导电电极进一步用焊膏层覆盖，使得多层陶瓷器件因此不经任何电镀步骤而制成，并且不需要处理废液镍或废液锡，并且没有引起环境污染的问题 通过电镀液，降低制造成本，缩短加工时间。

公开(公告)号：US20120135563A1

公开(公告)日：2012-05-31

申请号：US13298458

申请日：2011-11-17

Applicant: Ching-Hohn LIEN ,  Jie-An ZHU

Inventor： Ching-Hohn LIEN ,  Jie-An ZHU

IPC: H01L21/02

CPC classification number: H01C7/112 ,  H01C7/18

Abstract: A low-temperature firing process is available for cost saving to produce a multilayer chip ZnO varistor containing pure silver (Ag) formed as internal electrodes and calcined at ultralow firing temperature of 850-900° C., which process comprises: a) individually preparing ZnO grains in advance doped with doping ions for promotion of semi-conductivity of ZnO grains if calcined; b) individually preparing a desired high-impedance sintering material to be fired as grain boundaries to encapsulate ZnO grains; c) mixing the doped ZnO grains of Step a) with the high-impedance sintering material of Step b) in a predetermined ratio to form a mixture and proceeding with an initial sintering to have the mixture sintered and ground as composite ZnO ceramic powders, and d) processing the sintered mixture of Step c) to make multilayer chip ZnO varistors containing pure silver (Ag) internal electrodes but sintered at ultralow firing temperature of 850-900° C.

Abstract translation: 低成本焙烧工艺可以节约成本，生产出一种含有形成内部电极的纯银（Ag）的多层芯片ZnO压敏电阻，并在850-900℃的超低烧结温度下煅烧，该方法包括：a）单独制备 预先掺杂掺杂离子的ZnO晶粒，如果煅烧，则促进ZnO晶粒的半导电性; b）单独制备待烧结的期望的高阻抗烧结材料作为晶界以包封ZnO颗粒; c）将步骤a）的掺杂ZnO晶粒与步骤b）的高阻抗烧结材料以预定比例混合，形成混合物，并进行初始烧结，将混合物烧结并研磨为复合ZnO陶瓷粉末; d）加工步骤c）的烧结混合物以制备含有纯银（Ag）内部电极但在850-900℃的超低烧结温度下烧结的多层片状ZnO压敏电阻

公开(公告)号：US20070273469A1

公开(公告)日：2007-11-29

申请号：US11440064

申请日：2006-05-25

Applicant: Wei-Cheng Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang

Inventor： Wei-Cheng Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang

IPC: H01C7/10

CPC classification number: H01C7/10 ,  H01C7/112 ,  H01C7/18

Abstract: A multilayer zinc oxide varistor without bismuth oxide system ingredients, and having variable breakdown voltages by controlling the thickness of the ceramic material; the varistor is bismuth-free and composed of zinc oxide as the primary constituent with alkaline earth element (Ba) as first additive, at least one of transition elements of Mn, Co, Cr, or Ni as second additives, at least one of rare earth elements of Pr, La, Ce, Nd or Tb as third additives and at least one of B, Si, Se, Al, Ti, W, Sn, Sb, Na, or K as rest additives, and the bismuth-free and zinc oxide based varistor exhibits an excellent ESD (Electro-Static Discharge) withstanding characteristic.

Abstract translation: 一种不含氧化铋体系成分的多层氧化锌压敏电阻，通过控制陶瓷材料的厚度具有可变的击穿电压; 所述变阻器是无铋的，以氧化锌为主要成分的碱土金属元素（Ba）作为第一添加剂，Mn，Co，Cr或Ni的过渡元素中的至少一种作为第二添加剂，至少一种稀有金属 作为第三添加剂的Pr，La，Ce，Nd或Tb的土元素，作为剩余添加剂的B，Si，Se，Al，Ti，W，Sn，Sb，Na或K中的至少一种， 基于氧化锌的变阻器具有优异的ESD（静电放电）耐受特性。