公开(公告)号：US20230069864A1

公开(公告)日：2023-03-09

申请号：US17894579

申请日：2022-08-24

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Yuki MURAYAMA ,  Makoto KOSHIMIZU ,  Takahiro MORI ,  Junjiro SAKAI ,  Satoshi IIDA

IPC分类号： H01L21/4757 ,  H01L21/4763 ,  H01L21/475 ,  H01L23/31 ,  H01L23/532

摘要： There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.

公开(公告)号：US20220319583A1

公开(公告)日：2022-10-06

申请号：US17843241

申请日：2022-06-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Shih-Hao Lin

IPC分类号： G11C11/412 ,  H01L21/475 ,  H01L27/11 ,  G11C11/419

摘要： Semiconductor devices and methods are provided. A semiconductor device of the present disclosure includes a bias source, a memory cell array including a first region adjacent to the bias source and a second region away from the bias source, and a conductive line electrically coupled to the bias source, a first memory cell in the first region and a second memory cell in the second region. The first memory cell is characterized by a first alpha ratio and the second memory cell is characterized by a second alpha ratio smaller than the first alpha ratio.

公开(公告)号：US20220020867A1

公开(公告)日：2022-01-20

申请号：US17449607

申请日：2021-09-30

申请人： HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

发明人： Jun Liu ,  Luke Ding ,  Jingang Fang ,  Bin Zhou ,  Leilei Cheng ,  Wei Li

IPC分类号： H01L29/66 ,  H01L29/786 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/475 ,  H01L29/40 ,  H01L21/4757 ,  H01L27/12 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213

摘要： A manufacturing method of a display substrate, a display substrate, and a display device. The manufacturing method includes: forming an active layer; forming a gate insulation film layer, a gate film layer and a photoresist film layer; exposing the photoresist film layer to a light and developing the exposed photoresist film layer until the developed photoresist film layer has a thickness of 1.8-2.2 μm and a slope angle not less than 70°; over-etching the gate film layer to form a gate electrode, an orthographic projection of the gate electrode being located within a region of an orthographic projection of the developed photoresist film layer; over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer; peeling off the photoresist film layer remaining on a surface of the gate electrode; and performing a conductive treatment to the active layer.

公开(公告)号：US11211488B2

公开(公告)日：2021-12-28

申请号：US16716119

申请日：2019-12-16

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/475 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/417 ,  H01L29/786 ,  H01L29/06 ,  H01L21/461 ,  H01L29/775

摘要： An SGT is formed that includes Si pillars. The SGT includes WSi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.

公开(公告)号：US11183516B2

公开(公告)日：2021-11-23

申请号：US16266263

申请日：2019-02-04

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Hideomi Suzawa ,  Yuta Endo ,  Kazuya Hanaoka

IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L21/475 ,  H01L21/4757

摘要： A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a first insulating layer; a first oxide layer over the first insulating layer; a semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer over the semiconductor layer; a second insulating layer over the first insulating layer; a third insulating layer over the second insulating layer, the source electrode layer, and the drain electrode layer; a second oxide layer over the semiconductor layer; a gate insulating layer over the second oxide layer; a gate electrode layer over the gate insulating layer; and a fourth insulating layer over the third insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer.

公开(公告)号：US10566473B2

公开(公告)日：2020-02-18

申请号：US15961006

申请日：2018-04-24

申请人： LG ELECTRONICS INC.

发明人： Jinhee Park ,  Soohyun Kim

IPC分类号： H01L31/0224 ,  H01L21/02 ,  H01L31/0735 ,  H01L31/18 ,  H01L31/0693 ,  H01L31/0304 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/04 ,  H01L21/768 ,  H01L21/475

摘要： A compound semiconductor solar cell and a method of manufacturing the same are disclosed. The method for fabricating a compound semiconductor solar cell comprises forming a first mask layer on a front surface of a compound semiconductor layer of a second region which is a region other than a first region where the front electrode is to be formed; forming a seed metal layer on the front surface of the compound semiconductor layer of the first region and on the first mask layer of the second region; removing the seed metal layer over the first mask layer and the first mask layer; removing a part of the compound semiconductor layer of the second region from the front surface of the compound semiconductor layer by using the seed metal layer of the first region as a mask; forming a second mask layer on the compound semiconductor layer of the second region; forming an electrode metal layer on the seed metal layer not covered by the second mask layer; and removing the second mask layer.

公开(公告)号：US10312150B1

公开(公告)日：2019-06-04

申请号：US15919594

申请日：2018-03-13

申请人： GLOBALFOUNDRIES Inc.

发明人： Fuad Al-Amoody ,  Jinping Liu ,  Joseph Kassim ,  Bharat Krishnan

IPC分类号： H01L21/8234 ,  H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78 ,  H01L21/475 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

摘要： Methods of forming a fin-type field-effect transistor. A gate structure is formed that extends across a plurality of semiconductor fins. A spacer layer composed of a dielectric material is conformally deposited over the gate structure, the semiconductor fins, and a dielectric layer in gaps between the semiconductor fins. A protective layer is conformally deposited over the spacer layer. The protective layer over the dielectric layer in the gaps between the semiconductor fins is masked, and the protective layer is then removed from the gate structure and the semiconductor fins selective to the dielectric material of the spacer layer.

公开(公告)号：US10263015B2

公开(公告)日：2019-04-16

申请号：US15443079

申请日：2017-02-27

申请人： Japan Display Inc.

发明人： Toshinari Sasaki

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L21/475 ,  H01L29/423 ,  H01L29/66

摘要： A semiconductor device includes a first electrode, a first insulating layer on the first electrode, a second electrode on the first insulating layer, a second insulating layer on the second electrode, a first opening in the first insulating layer, the second electrode and the second insulating layer, the first opening reaching the first electrode, a first oxide semiconductor layer in the first opening, the first oxide semiconductor layer being connected with the first electrode and the second electrode, a first gate electrode facing the first oxide semiconductor layer, and a first gate insulating layer between the first oxide semiconductor layer and the first gate electrode.

公开(公告)号：US20190074185A1

公开(公告)日：2019-03-07

申请号：US16103025

申请日：2018-08-14

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： Hidehiko KARASAKI ,  Noriyuki MATSUBARA ,  Atsushi HARIKAI ,  Hidefumi SAEKI

IPC分类号： H01L21/3065 ,  B23K26/0622 ,  H01L21/67 ,  H01L21/02 ,  H01L21/475

摘要： Method of manufacturing an element chip which can suppress residual debris in plasma dicing. A back surface of a semiconductor wafer is held on a dicing tape. Then, a surface of the wafer is coated with a mask that includes a water-insoluble lower mask and a water-soluble upper mask. Subsequently, an opening is formed in the mask by irradiating the mask with laser light to expose a dividing region. Then, the semiconductor wafer is caused to come into contact with water to remove the upper mask covering each of the element regions while leaving the lower layer. After that, the wafer is exposed to plasma to perform etching on the dividing region exposed from the opening until the etching reaches the back surface, thereby dicing the semiconductor wafer into a plurality of element chips. Thereafter, the lower layer mask left on the front surface of the semiconductor chips is removed.

公开(公告)号：US20180159066A1

公开(公告)日：2018-06-07

申请号：US15525500

申请日：2015-12-17

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Yi KONG ,  Junhao LIU ,  Hongwei XUE ,  Qingsong XU ,  Lu LIU

IPC分类号： H01L51/52 ,  H01L21/70 ,  H01L21/475 ,  H01L27/12

摘要： An array substrate, a display panel, a display device, a method for manufacturing the array substrate and a method for manufacturing the display panel are provided. The array substrate includes a base substrate, and an organic layer and a passivation layer arranged above the base substrate. The base substrate includes a display region and a non-display region surrounding the display region. Each of the organic layer and the passivation layer is arranged in both the display region and the non-display region. A groove is arranged in the organic layer and the passivation layer in the non-display region, the groove penetrates the organic layer and the passivation layer and is of a closed pattern surrounding the display region. The groove is to be filled with a sealing material.