公开(公告)号：WO2004030049A3

公开(公告)日：2005-01-27

申请号：PCT/US0329978

申请日：2003-09-25

Applicant: TOKYO ELECTRON LTD ,  CHEN LEE ,  LUDVIKSSON AUDUNN

Inventor： CHEN LEE ,  LUDVIKSSON AUDUNN

IPC: B44C1/22 ,  C03C15/00 ,  C23F1/00 ,  H01L21/00 ,  H01L21/311 ,  H01L21/461 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/67069 ,  H01L21/67253 ,  H01L29/51 ,  H01L29/517

Abstract: A system and a method to remove a layer of high-k dielectric material during the manufacturing of an integrated circuit. In one embodiment of the invention, an etch reactant is employed to form volatile etch products when reacted with high-k layers. Alternately, high-k layers can be anisotropically etched of in accordance with a patterned photoresist or hard mask, where a hyperthermal beam of neutral atoms is used to aid in the reaction of an etch reactant with a high-k layer. Alternately, a hyperthermal beam of neutral atoms or a plasma treatment can used to modify a high-k layer, and subsequently etch the modified high-k layer utilizing an etch reactant that reacts with the modified high-k layer. In still another embodiment of the invention, the hyperthermal beam of neutral atoms is used to etch a high-k layer through physical bombardment of the high-k layer.

Abstract translation: 在制造集成电路期间去除高k电介质材料层的系统和方法。 在本发明的一个实施方案中，当与高k层反应时，使用蚀刻反应物形成挥发性蚀刻产物。 或者，高k层可以根据图案化的光致抗蚀剂或硬掩模进行各向异性蚀刻，其中使用中性原子的超热束来帮助蚀刻反应物与高k层的反应。 或者，可以使用中性原子的超热束或等离子体处理来修饰高k层，随后使用与修饰的高k层反应的蚀刻反应物蚀刻修饰的高k层。 在本发明的另一个实施例中，使用中性原子的超热束来通过物理轰击高k层蚀刻高k层。

公开(公告)号：WO2004030069A2

公开(公告)日：2004-04-08

申请号：PCT/SG2003/000220

申请日：2003-09-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LIAN, Jenny ,  ZHUANG, Haoren ,  EGGER, Ulrich ,  HORNIK, Karl

IPC: H01L21/311

CPC classification number: H01L28/55 ,  H01L21/31122

Abstract: A method of forming a ferroelectric capacitor, in particular for use in a FeRAM or high-k DRAM application, and a capacitor made by the method. The method comprises forming a first layer which is patterned, for example by a reactive ion etching method. A ferroelectric material is then formed over the patterned first layer. The morphology of the ferroelectric material will be dependent upon the patterning of the first layer. The ferroelectric layer is then patterned, for example using a wet etching or a reactive ion etching method. The etching will depend upon the morphology of the ferroelectric layer. After etching the ferroelectric layer, a conductive layer is provided over the ferroelectric layer to form a first electrode of the capacitor. If the first layer is a conductive layer, this forms the second electrode. If the first layer is a non-conductive layer,. the conductive layer is patterned to form both the first and second electrodes.

Abstract translation: 一种形成铁电电容器的方法，特别是用于FeRAM或高k DRAM应用中的方法以及由该方法制造的电容器。 该方法包括形成例如通过反应离子蚀刻方法图案化的第一层。 然后在图案化的第一层上形成铁电材料。 铁电材料的形态将取决于第一层的图案化。 然后，例如使用湿法蚀刻或反应离子蚀刻方法将铁电层图案化。 蚀刻将取决于铁电层的形态。 在腐蚀铁电层之后，在铁电层上提供导电层以形成电容器的第一电极。 如果第一层是导电层，则这形成第二电极。 如果第一层是非导电层， 图案化导电层以形成第一和第二电极。

公开(公告)号：WO2004001799A3

公开(公告)日：2004-03-25

申请号：PCT/US0319250

申请日：2003-06-18

Applicant: APPLIED MATERIALS INC

Inventor： LIU WEI ,  LILL THORSTEN B ,  MUI DAVID S L ,  BENCHER CHRISTOPHER DENNIS

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336

CPC classification number: H01L21/31122 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/66583

Abstract: A method for fabricating features on a substrate having reduced dimensions. The features are formed by defining a first mask (229) on regions of the substrate. The first mask is defined using lithographic techniques. A second mask (214) is then conformably formed on one or more sidewalls of the first mask. The features are formed on the substrate by removing the first mask and then etching the substrate using the second mask as an etch mask.

Abstract translation: 一种在尺寸减小的基板上制造特征的方法。 通过在衬底的区域上限定第一掩模（229）来形成特征。 第一个掩模使用光刻技术定义。 然后，第二掩模（214）顺应地形成在第一掩模的一个或多个侧壁上。 通过去除第一掩模在衬底上形成特征，然后使用第二掩模作为蚀刻掩模蚀刻衬底。

公开(公告)号：WO2004021409A2

公开(公告)日：2004-03-11

申请号：PCT/US2003/026496

申请日：2003-08-26

Applicant: TOKYO ELECTRON LIMITED ,  BEASE, Gordon ,  CHEN, Lee

Inventor： BEASE, Gordon ,  CHEN, Lee

IPC: H01L21/00

CPC classification number: H01L21/31122 ,  H01L21/31111

Abstract: A method and system are disclosed for modifying a layer of high-k material using a plasma process. The plasma process leads to enhanced removal rates of the modified high-k dielectric material using wet etching. The plasma process modifies the layer of high-k material through exposure to the plasma, where the plasma can comprise inert gases and/or reactive gases. The plasma treatment can be implemented as a step performed at the end of a gate-electrode etch process, or as a step at the end of a spacer-etch process.

Abstract translation: 公开了一种使用等离子体工艺来修饰高k材料层的方法和系统。 等离子体处理导致使用湿蚀刻改进的高k电介质材料的去除速率得到提高。 等离子体工艺通过暴露于等离子体来改变高k材料层，其中等离子体可以包含惰性气体和/或反应性气体。 等离子体处理可以实现为在栅电极蚀刻工艺结束时执行的步骤，或者作为在间隔物蚀刻工艺结束时的步骤。

公开(公告)号：WO03012851A3

公开(公告)日：2003-04-24

申请号：PCT/US0224346

申请日：2002-07-31

Applicant: APPLIED MATERIALS INC

Inventor： YAMAUCHI HIDEYUKI

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/8246 ,  H01L27/105

CPC classification number: H01L21/31122 ,  H01L28/55

Abstract: A method of etching a ferroelectric layer comprises etching a ferroelectric layer using boron trichloride gas and at least one auxiliary gas selected from the group consisting of a carbon-containing gas and a nitrogen-containing gas. The carbon-containing gas may include CHF3 or C2H4. The nitrogen-containing gas may include N2 or NF3. The method reduces side etching of ferroelectric layers, and in particular, PZT-based ferroelectric layers and thereby improves electrical performance and reliability of devices made therefrom.

Abstract translation: 一种蚀刻铁电层的方法包括使用三氯化硼气体和从由含碳气体和含氮气体组成的组中选择的至少一种辅助气体蚀刻铁电层。 含碳气体可以包括CHF 3或C 2 H 4。 含氮气体可以包括N 2或NF 3。 该方法减少铁电层，特别是PZT基铁电层的侧面蚀刻，从而改善由其制成的器件的电性能和可靠性。

公开(公告)号：WO2002073687A2

公开(公告)日：2002-09-19

申请号：PCT/US2002/003807

申请日：2002-02-08

Applicant: MOTOROLA, INC.

Inventor： MUI, Kok, Wai ,  HARUN, Fuaida, Bte ,  TAN, Lan, Chu ,  MOHD NOR, Mohd, Faizairi, Bin

IPC: H01L21/60

CPC classification number: H01L24/05 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/32134 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/0381 ,  H01L2224/04042 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2224/73265 ,  H01L2224/85011 ,  H01L2224/85013 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  Y10S438/905 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A method of preparing a semiconductor wafer having a integrated circuits formed on it that have pads formed of copper includes the steps of removing oxide from the copper pads and then the vacuum packing the wafer in a shock-proof container. The oxide may be removed from the copper pads in a number of ways. A first way includes cleaning the wafer in an alkaline solution, performing acid neutralization on the cleaned wafer, and then drying the wafer. A second way includes cleaning the wafer with an acid solution, rinsing the acid cleaned wafer with water, applying an anti-oxidant activator to the surface of the copper pads, rinsing the wafer with water after the application of the anti-oxidant activator, and then drying the water rinsed wafer. Yet a third way includes plasma cleaning the copper pads using a combination of about 5-10% Hydrogen and about 90-95% Argon and then sputtering a very thin layer of aluminum on a surface of the copper pads. The layer of aluminum has a thickness of about 1-5 nanometers.

Abstract translation: 制备具有形成在其上的具有由铜形成的焊盘的集成电路的半导体晶片的方法包括以下步骤：从铜焊盘去除氧化物，然后将晶片真空包装在防震容器中。 可以以多种方式从铜焊盘去除氧化物。 第一种方法包括在碱性溶液中清洗晶片，在清洁的晶片上进行酸中和，然后干燥晶片。 第二种方法包括用酸溶液清洗晶片，用水冲洗酸洗的晶片，将抗氧化剂活化剂施加到铜垫的表面上，在施用抗氧化剂活化剂之后用水冲洗晶片;以及 然后干燥水冲洗的晶片。 第三种方法包括使用约5-10％氢气和约90-95％氩气的组合等离子体清洗铜焊盘，然后在铜焊盘的表面上溅射非常薄的铝层。 铝层的厚度约为1-5纳米。

公开(公告)号：WO02037557A2

公开(公告)日：2002-05-10

申请号：PCT/EP2001/011076

申请日：2001-09-25

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/3205

CPC classification number: H01L28/40 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a method for producing an integrated circuit, comprising the following steps: a circuit substrate (1) is prepared; a first metallising area (10a) and a second metallising area (10b) consisting of a first metal are provided in the circuit substrate (1); an intermediate layer (15) is provided over the first metallising area (10a) and the second metallising area (10b); the intermediate layer (15) over the first metallising area (10a) is removed by etching, an oxide film (100) being simultaneously formed on the surface of the first metallising area (10a); and the oxide film (100) on the surface of the first metallising area (10a) is at least partially transformed so that a conductive compound is created from the first metal, by means of the oxide film (100), forming a connection to the first metallising area (10a) on the surface of the resulting structure.

Abstract translation: 本发明提供了一种制造包括：提供电路基板（1）的步骤的集成电路的方法; 提供第一金属化（10a）和第一金属的在电路基板（1）的第二金属化（图10b）; 在第一金属化（10a）和所述第二金属化提供了中间层（15）（图10b）; 通过蚀刻工艺具有氧化物膜（100）的所述第一金属化（10A）的表面上同时形成去除在所述第一金属化（10A）的中间层（15）; 和第一金属化（10A）的表面上至少部分地将所述氧化膜（100），从而通过氧化膜（100）中的第一金属的导电连接形成，其具有将所得的表面上的第一金属化（10A）的连接 形成结构。

公开(公告)号：WO0049649A3

公开(公告)日：2000-12-07

申请号：PCT/US0004019

申请日：2000-02-16

Applicant: APPLIED MATERIALS INC

Inventor： HWANG JENG H ,  CHIANG KANG-LIE ,  JIN GUANGXIANG

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/02071 ,  H01L21/31122 ,  H01L28/55 ,  H01L28/60

Abstract: Method for removing or inactivating corrosion-forming etch residues remaining on the surface of a dielectric material after etching a metal layer which is supported by the dielectric material. The surface of the dielectric material which supports the corrosion-forming etch residues is post-etch treated in order to remove the corrosion-forming etch residues. Post-etch treating of the surface of the dielectric material includes disposing the dielectric material in a vacuum chamber having microwave downstream treating gas plasma, or contacting the surface of the dielectric material with deionized water.

Abstract translation: 在蚀刻由电介质材料支撑的金属层之后去除或钝化保留在电介质材料表面上的腐蚀形成蚀刻残余物的方法。 支撑腐蚀形成腐蚀残留物的介电材料表面被腐蚀后处理以除去腐蚀形成腐蚀残留物。 介电材料表面的蚀刻后处理包括将介电材料设置在具有微波下游处理气体等离子体的真空室中，或者将介电材料的表面与去离子水接触。

公开(公告)号：WO2018236614A1

公开(公告)日：2018-12-27

申请号：PCT/US2018/036934

申请日：2018-06-11

Applicant: LAM RESEARCH CORPORATION

Inventor： GUHA, Joydeep ,  REDDY, Sirish K. ,  CHATTOPADHYAY, Kaushik ,  MOUNTSIER, Thomas W. ,  EPPLER, Aaron ,  LILL, Thorsten ,  VAHEDI, Vahid ,  SINGH, Harmeet

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/3065 ,  H01L21/033

CPC classification number: H01L21/31144 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76802

Abstract: A method for etching features in an OMOM stack with first layer of silicon oxide, a second layer of a metal containing material over the first layer, a third layer of silicon oxide over the second layer, and a fourth layer of a metal containing material over the third layer is provided. A hardmask is formed over the stack. The hardmask is patterned. The OMOM stack is etched through the hardmask.

公开(公告)号：WO2018080712A1

公开(公告)日：2018-05-03

申请号：PCT/US2017/053802

申请日：2017-09-27

Applicant: APPLIED MATERIALS, INC.

Inventor： CHANG, Chih-Yang ,  HUNG, Raymond Hoiman ,  SATO, Tatsuya E. ,  KIM, Nam Sung ,  SUN, Shiyu ,  WOOD, Bingxi Sun

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/7851 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32134 ,  H01L21/32136 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7853

Abstract: Embodiments disclosed herein relate to an improved transistor with reduced parasitic capacitance. In one embodiment, the transistor device includes a three-dimensional fin structure protruding from a surface of a substrate, the three-dimensional fin structure comprising a top surface and two opposing sidewalls, a first insulating layer formed on the two opposing sidewalls of the three-dimension fin structure, a sacrificial spacer layer conformally formed on the first insulating layer, wherein the sacrificial spacer layer comprises an aluminum oxide based material or a titanium nitride based material, and a second insulating layer conformally formed on the sacrificial spacer layer.

Abstract translation: 这里公开的实施例涉及具有减小的寄生电容的改进的晶体管。 在一个实施例中，所述晶体管器件包括从衬底的表面突出的三维鳍结构，所述三维鳍结构包括顶表面和两个相对的侧壁，第一绝缘层形成在所述三个 所述牺牲间隔层共形地形成在所述第一绝缘层上，其中所述牺牲间隔层包括氧化铝基材料或氮化钛基材料以及共形地形成在所述牺牲间隔层上的第二绝缘层。 p>