公开(公告)号：WO2014205907A1

公开(公告)日：2014-12-31

申请号：PCT/CN2013/081888

申请日：2013-08-20

Applicant: TSINGHUA UNIVERSITY

Inventor： WANG, Jing ,  LIANG, Renrong ,  XU, Jun

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66628 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A field effect transistor and a method for forming the same are provided. The field effect transistor comprises: a substrate (100); an ultra-thin insulator layer (200) formed on the substrate (100), wherein a material of the ultra-thin insulator layer (200) is a monocrystalline rare earth oxide or a monocrystalline beryllium oxide; an ultra-thin semiconductor monocrystalline film (300) formed on the ultra-thin insulator layer (200); and a gate stack (400) formed on the ultra-thin semiconductor monocrystalline film (300), and comprising a gate dielectric (410) and a gate electrode (420) formed on the gate dielectric (410).

Abstract translation: 提供场效应晶体管及其形成方法。 场效应晶体管包括：衬底（100）; 形成在所述基板（100）上的超薄绝缘体层（200），其中所述超薄绝缘体层（200）的材料为单晶稀土氧化物或单晶氧化铍; 形成在超薄绝缘体层（200）上的超薄半导体单晶膜（300）; 以及形成在所述超薄半导体单晶膜（300）上的栅堆叠（400），并且包括形成在所述栅极电介质（410）上的栅极电介质（410）和栅电极（420）。

公开(公告)号：WO2013177855A1

公开(公告)日：2013-12-05

申请号：PCT/CN2012/078789

申请日：2012-07-18

Applicant: TSINGHUA UNIVERSITY ,  WANG, Wei ,  WANG, Jing ,  GUO, Lei

Inventor： WANG, Wei ,  WANG, Jing ,  GUO, Lei

IPC: H01L29/04 ,  H01L21/335

CPC classification number: H01L29/7849 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78684

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate (100); a rare earth oxide layer (200) formed on the semiconductor substrate (100); a channel region (300) formed on the rare earth oxide layer (200); and a source region (400) and a drain region (500) formed at both sides of the channel region (300) respectively, in which a relationship between a lattice constant a of the rare earth oxide layer (200) and a lattice constant b of a semiconductor material of the channel region (300) and/or the source region (400) and the drain region (500) is a = (n ± c)b, where n is an integer, c is a mismatch ratio of lattice constants, and 0

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括：半导体衬底（100）; 形成在半导体衬底（100）上的稀土氧化物层（200）; 形成在所述稀土氧化物层（200）上的沟道区（300）。 以及分别形成在沟道区（300）的两侧的源区（400）和漏区（500），其中稀土氧化物层（200）的晶格常数a与晶格常数b 沟道区域（300）和/或源极区域（400）和漏极区域（500）的半导体材料是a =（n±c）b，其中n是整数，c是晶格的失配比 常数，0

公开(公告)号：WO2012163047A1

公开(公告)日：2012-12-06

申请号：PCT/CN2011/082110

申请日：2011-11-11

Applicant: TSINGHUA UNIVERSITY ,  WANG, Jing ,  GUO, Lei

Inventor： WANG, Jing ,  GUO, Lei

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/764 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate (1100); a plurality of convex structures (1200) formed on the substrate (1100), in which every two adjacent convex structures (1200) are separated by a cavity; a plurality of floated films (1300), in which each floated film (1300) is formed between the every two adjacent convex structures (1200) and connected with tops of the every two adjacent convex structures (1200), the floated films (1300) are partitioned into a plurality of sets, a channel layer is formed on a convex structure (1200) between the floated films (1300) in each set, a source region and a drain region are formed on two sides of the channel layer respectively, and an isolation portion (1200) is set between two adjacent sets of floated films (1300); and a gate stack (1400) formed on each channel layer.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括：衬底（1100）; 形成在所述基板（1100）上的多个凸起结构（1200），其中每两个相邻凸起结构（1200）由空腔分隔开; 多个浮动膜（1300），其中每个浮动膜（1300）形成在每两个相邻的凸起结构（1200）之间并与每两个相邻凸起结构（1200）的顶部连接，浮动膜（1300） 被划分为多组，在每组中的浮动膜（1300）之间的凸形结构（1200）上形成沟道层，在沟道层的两侧分别形成源极区和漏极区，以及 隔离部分（1200）设置在两组相邻的漂浮膜（1300）之间; 和形成在每个沟道层上的栅叠层（1400）。

公开(公告)号：WO2012116529A1

公开(公告)日：2012-09-07

申请号：PCT/CN2011/076342

申请日：2011-06-24

Applicant: TSINGHUA UNIVERSITY ,  CUI, Ning ,  LIANG, Renrong ,  WANG, Jing ,  XU, Jun

Inventor： CUI, Ning ,  LIANG, Renrong ,  WANG, Jing ,  XU, Jun

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7391 ,  H01L21/26586

Abstract: The present disclosure provides a tunneling device, which comprises: a substrate (1100); a channel region (1300) formed in the substrate, and a source region (1500) and a drain region (1400) formed on two sides of the channel region (1300); and a gate stack (1600) formed on the channel region (1300) and a first side wall (1910) and a second side wall (1920) formed on two sides of the gate stack (1600), wherein the gate stack (1600) comprises: a first gate dielectric layer (1631); at least a first gate electrode (1610) and a second gate electrode (1620) formed on the first gate dielectric layer (1631); a second gate dielectric layer (1632) formed between the first gate electrode (1610) and the first side wall (1910); and a third gate dielectric layer (1633) formed between the second gate electrode (1620) and the second side wall (1920).

Abstract translation: 本公开提供一种隧道装置，其包括：基板（1100）; 形成在所述基板中的沟道区域（1300），以及形成在所述沟道区域（1300）的两侧的源极区域（1500）和漏极区域（1400）。 以及形成在所述沟道区域（1300）上的栅极堆叠（1600）和形成在所述栅极堆叠（1600）的两侧上的第一侧壁（1910）和第二侧壁（1920），其中所述栅极堆叠（1600） 包括：第一栅介质层（1631）; 形成在所述第一栅极介电层（1631）上的至少第一栅电极（1610）和第二栅电极（1620）。 形成在第一栅电极（1610）和第一侧壁（1910）之间的第二栅介质层（1632）; 和形成在第二栅电极（1620）和第二侧壁（1920）之间的第三栅介质层（1633）。

公开(公告)号：WO2012163049A1

公开(公告)日：2012-12-06

申请号：PCT/CN2011/082112

申请日：2011-11-11

Applicant: TSINGHUA UNIVERSITY ,  WANG, Jing ,  GUO, Lei

Inventor： WANG, Jing ,  GUO, Lei

IPC: H01L29/06 ,  H01L29/24 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/778 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/66431

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a Si substrate (1100); a plurality of convex structures (1200) formed on the Si substrate (1100), in which every two adjacent convex structures (1200) are separated by a cavity in a predetermined pattern, and the cavity between every two adjacent convex structures (1200) is less than 50nm in width; a first semiconductor film (1300), in which the first semiconductor film (1300) is formed between the every two adjacent convex structures (1200) and connected with tops of the every two adjacent convex structures (1200); a buffer layer (2100) formed on the first semiconductor film (1300); and a high-mobility III-V compound semiconductor layer (2000) formed on the buffer layer (2100).

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括：Si衬底（1100）; 形成在Si衬底（1100）上的多个凸起结构（1200），其中每两个相邻凸起结构（1200）以预定图案被空腔隔开，并且每两个相邻凸起结构（1200）之间的空腔是 宽度小于50nm; 第一半导体膜（1300），其中第一半导体膜（1300）形成在每两个相邻的凸起结构（1200）之间并与每两个相邻凸起结构（1200）的顶部连接; 形成在所述第一半导体膜（1300）上的缓冲层（2100）; 和形成在缓冲层（2100）上的高迁移率III-V族化合物半导体层（2000）。

公开(公告)号：WO2012129894A1

公开(公告)日：2012-10-04

申请号：PCT/CN2011/079442

申请日：2011-09-07

Applicant: TSINGHUA UNIVERSITY ,  WANG, Jing ,  XU, Jun ,  GUO, Lei

Inventor： WANG, Jing ,  XU, Jun ,  GUO, Lei

IPC: H01L21/20 ,  H01L29/161

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02658 ,  H01L29/1054

Abstract: A semiconductor structure is provided, comprising: a Si substrate (1100); a porous structure layer (1200) formed on the Si substrate (1100), in which the porous structure layer (1200) has a flat surface and comprises a Si 1-x Ge x layer with low Ge content; and a Ge-containing layer (1300) formed on the porous structure layer (1200), in which the Ge-containing layer (1300) comprises a Ge layer or a Si 1-y Ge y layer with high Ge content and x≤y. Further, a method for forming the semiconductor structure is also provided.

Abstract translation: 提供一种半导体结构，包括：Si衬底（1100）; 形成在所述Si衬底（1100）上的多孔结构层（1200），其中所述多孔结构层（1200）具有平坦表面并且包括具有低Ge含量的Si 1-x Ge x层; 和形成在所述多孔结构层（1200）上的含Ge层，其中所述含Ge层包括Ge层或具有高Ge含量且x = y的Si1-yGey层。 此外，还提供了一种用于形成半导体结构的方法。

公开(公告)号：WO2014161231A1

公开(公告)日：2014-10-09

申请号：PCT/CN2013/077256

申请日：2013-06-14

Applicant: TSINGHUA UNIVERSITY

Inventor： ZHAO, Mei ,  LIANG, Renrong ,  WANG, Jing ,  XU, Jun

IPC: H01L21/28

CPC classification number: H01L29/165 ,  H01L21/28255 ,  H01L29/161 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method for forming a semiconductor gate structure and a semiconductor gate structure are provided. The method comprises: providing a substrate with a Ge layer as a surface thereof; forming a Sn layer on the Ge layer, in which an interface between the Ge layer and the Sn layer is a GeSn layer; removing the Sn layer to expose the GeSn layer; forming a GeSnO x passivation layer by performing an oxidation treatment for the GeSn layer, or forming a GeSnN or GeSnON passivation layer by performing a passivation treatment for the GeSn layer; and forming a gate stack on the GeSnO x , GeSnN or GeSnON passivation layer.

Abstract translation: 提供一种形成半导体栅极结构和半导体栅极结构的方法。 该方法包括：提供具有Ge层作为其表面的衬底; 在Ge层上形成Sn层，其中Ge层和Sn层之间的界面是GeSn层; 去除Sn层以暴露GeSn层; 通过对GeSn层进行氧化处理，或者通过对GeSn层进行钝化处理形成GeSnN或GeSnON钝化层来形成GeSnOx钝化层; 并在GeSnOx，GeSnN或GeSnON钝化层上形成栅叠层。

公开(公告)号：WO2012163046A1

公开(公告)日：2012-12-06

申请号：PCT/CN2011/082109

申请日：2011-11-11

Applicant: TSINGHUA UNIVERSITY ,  WANG, Jing ,  GUO, Lei

Inventor： WANG, Jing ,  GUO, Lei

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/336

CPC classification number: H01L21/02378 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66651 ,  H01L29/78

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a wafer (1100); a plurality of convex structures (1200) formed on the wafer (1100), in which every two adjacent convex structures (1200) are separated by a cavity in a predetermined pattern and arranged in an array, and the cavity between every two adjacent convex structures is less than 50nm in width; and a first semiconductor film (1300) formed on the plurality of convex structures (1200), in which a part of the first semiconductor film (1300) is spaced apart from the wafer (1100).

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括：晶片（1100）; 形成在所述晶片（1100）上的多个凸起结构（1200），其中每两个相邻凸起结构（1200）以预定图案以预定图案分隔并排列成阵列，并且每两个相邻凸起结构之间的空腔 宽度小于50nm; 以及形成在所述多个凸起结构（1200）上的第一半导体膜（1300），其中所述第一半导体膜（1300）的一部分与所述晶片（1100）间隔开。

公开(公告)号：WO2012155392A1

公开(公告)日：2012-11-22

申请号：PCT/CN2011/077934

申请日：2011-08-02

Applicant: TSINGHUA UNIVERSITY ,  ZHAO, Mei ,  LIANG, Renrong ,  WANG, Jing ,  XU, Jun

Inventor： ZHAO, Mei ,  LIANG, Renrong ,  WANG, Jing ,  XU, Jun

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L21/265 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/265 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/7833

Abstract: A semiconductor structure is provided. The semiconductor structure comprises: a substrate (1); a gate dielectric layer (20) formed on the substrate; a metal gate electrode layer (30) formed on the gate dielectric layer (20); and at least one metal-containing adjusting layer (43) for adjusting a work function of the semiconductor structure, in which an interfacial layer (10) is formed between the substrate (1) and the gate dielectric layer (20), and an energy of bond between a metal atom in the metal-containing adjusting layer (43) and an oxygen atom is larger than that between an atom of materials forming the gate dielectric layer (20) or the interfacial layer (10) and an oxygen atom. Further, a method for forming the semiconductor structure is also provided.

Abstract translation: 提供半导体结构。 半导体结构包括：衬底（1）; 形成在所述基板上的栅介质层（20）; 形成在栅介质层（20）上的金属栅电极层（30）; 以及至少一个用于调节半导体结构的功函数的含金属的调节层（43），其中在基板（1）和栅介质层（20）之间形成界面层（10），并且能量 含金属的调整层（43）中的金属原子与氧原子之间的键合大于形成栅极介电层（20）或界面层（10）的材料的原子与氧原子之间的键合。 此外，还提供了一种用于形成半导体结构的方法。

公开(公告)号：WO2012119418A1

公开(公告)日：2012-09-13

申请号：PCT/CN2011/078946

申请日：2011-08-25

Applicant: TSINGHUA UNIVERSITY ,  WANG, Jing ,  XU, Jun ,  GUO, Lei

Inventor： WANG, Jing ,  XU, Jun ,  GUO, Lei

IPC: H01L21/336 ,  H01L21/20

CPC classification number: H01L21/76283 ,  H01L21/76251 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/78684

Abstract: A strained Ge-on-insulator structure is provided, comprising: a silicon substrate (1100), in which an oxide insulating layer (1200) is formed on a surface of the silicon substrate (1100); a Ge layer (1300) formed on the oxide insulating layer (1200), in which a first passivation layer (1400) is formed between the Ge layer (1300) and the oxide insulating layer (1200); a gate stack (1600, 1700) formed on the Ge layer (1300), a channel region formed below the gate stack (1600, 1700), and a source (1800) and a drain (1800) formed on sides of the channel region; and a plurality of shallow trench isolation structures (1900) extending into the silicon substrate (1100) and filled with an insulating dielectric material to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.

Abstract translation: 提供了一种应变绝缘体上的结构，包括：在硅衬底（1100）的表面上形成氧化物绝缘层（1200）的硅衬底（1100）; 形成在氧化物绝缘层（1200）上的Ge层（1300），其中在Ge层（1300）和氧化物绝缘层（1200）之间形成第一钝化层（1400）; 形成在Ge层（1300）上的栅极堆叠（1600,1700），形成在栅极叠层（1600,1700）下方的沟道区域，以及形成在沟道区域侧面上的源极（1800）和漏极（1800） ; 以及多个浅沟槽隔离结构（1900），其延伸到硅衬底（1100）中并且填充有绝缘介电材料以在沟道区域中产生应变。 此外，还提供了用于形成应变的绝缘体上Ge的结构的方法。